summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
diff options
context:
space:
mode:
authorSteve Reinhardt <steve.reinhardt@amd.com>2015-04-22 20:22:29 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2015-04-22 20:22:29 -0700
commit0cf36d94095aedef3c51447243c5a3cc14dd5d56 (patch)
treec0ed9e35fbbc5512f7fedf2947d4ae2702214f8e /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
parenta70a83155bfe4c3877894c29f9dea720beb40f9c (diff)
downloadgem5-0cf36d94095aedef3c51447243c5a3cc14dd5d56.tar.xz
stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout')
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout13
1 files changed, 6 insertions, 7 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 09918a5fe..e4986f157 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,15 +1,14 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 11:22:42
-gem5 started Jun 21 2014 11:25:19
+gem5 compiled Apr 22 2015 10:58:25
+gem5 started Apr 22 2015 14:33:28
gem5 executing on phenom
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0
- 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0
+ 0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0
+ 0: system.cpu.isa: ISA system set to: 0 0x38f90a0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16786000 because target called exit()
+Exiting @ tick 17307500 because target called exit()