diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 2538 |
1 files changed, 1269 insertions, 1269 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index b3c6058a4..306010dfa 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,1273 +1,1273 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18517500 # Number of ticks simulated -final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74881 # Simulator instruction rate (inst/s) -host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301872470 # Simulator tick rate (ticks/s) -host_mem_usage 270416 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 10 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18432000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5212000 # Total ticks spent queuing -system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.69 # Data bus utilization in percentage -system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 329 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46545.45 # Average gap between requests -system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) -system.physmem_0.averagePower 659.559336 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) -system.physmem_1.averagePower 567.626569 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2820 # Number of BP lookups -system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups -system.cpu.branchPred.BTBHits 844 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 5391 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37036 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 40 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8207 # Type of FU issued -system.cpu.iq.rate 0.221595 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3007 # number of memory reference insts executed -system.cpu.iew.exec_branches 1490 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.212901 # Inst execution rate -system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7470 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3518 # num instructions producing a value -system.cpu.iew.wb_consumers 6872 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22825 # The number of ROB reads -system.cpu.rob.rob_writes 21580 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7779 # number of integer regfile reads -system.cpu.int_regfile_writes 4297 # number of integer regfile writes -system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28140 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3029 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4257 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits -system.cpu.icache.overall_hits::total 1587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses -system.cpu.icache.overall_misses::total 395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 102 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 102 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 102 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 102 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 38 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22791500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22791500 # number of ReadCleanReq miss cycles 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-system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 354 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +sim_seconds 0.000019 +sim_ticks 18517500 +final_tick 18517500 +sim_freq 1000000000000 +host_inst_rate 45460 +host_op_rate 53229 +host_tick_rate 183240261 +host_mem_usage 280812 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 +system.physmem.bytes_read::cpu.inst 17600 +system.physmem.bytes_read::cpu.data 7744 +system.physmem.bytes_read::total 25344 +system.physmem.bytes_inst_read::cpu.inst 17600 +system.physmem.bytes_inst_read::total 17600 +system.physmem.num_reads::cpu.inst 275 +system.physmem.num_reads::cpu.data 121 +system.physmem.num_reads::total 396 +system.physmem.bw_read::cpu.inst 950452275 +system.physmem.bw_read::cpu.data 418199001 +system.physmem.bw_read::total 1368651276 +system.physmem.bw_inst_read::cpu.inst 950452275 +system.physmem.bw_inst_read::total 950452275 +system.physmem.bw_total::cpu.inst 950452275 +system.physmem.bw_total::cpu.data 418199001 +system.physmem.bw_total::total 1368651276 +system.physmem.readReqs 396 +system.physmem.writeReqs 0 +system.physmem.readBursts 396 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 25344 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 25344 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 89 +system.physmem.perBankRdBursts::1 45 +system.physmem.perBankRdBursts::2 20 +system.physmem.perBankRdBursts::3 43 +system.physmem.perBankRdBursts::4 18 +system.physmem.perBankRdBursts::5 32 +system.physmem.perBankRdBursts::6 35 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 28 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 10 +system.physmem.perBankRdBursts::13 6 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 6 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+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 +system.cpu.toL2Bus.pkt_size::total 28288 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 440 +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 440 +system.cpu.toL2Bus.reqLayer0.occupancy 223000 +system.cpu.toL2Bus.reqLayer0.utilization 1.2 +system.cpu.toL2Bus.respLayer0.occupancy 439500 +system.cpu.toL2Bus.respLayer0.utilization 2.4 +system.cpu.toL2Bus.respLayer1.occupancy 223494 +system.cpu.toL2Bus.respLayer1.utilization 1.2 +system.membus.snoop_filter.tot_requests 396 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 +system.membus.trans_dist::ReadResp 354 +system.membus.trans_dist::ReadExReq 42 +system.membus.trans_dist::ReadExResp 42 +system.membus.trans_dist::ReadSharedReq 354 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 +system.membus.pkt_count::total 792 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 +system.membus.pkt_size::total 25344 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 396 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 396 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 396 +system.membus.reqLayer0.occupancy 484000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2091500 +system.membus.respLayer1.utilization 11.3 ---------- End Simulation Statistics ---------- |