diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-03-09 09:39:09 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-03-09 09:39:09 -0500 |
commit | 99fb8f81407efa54008ddf443718e492f583b142 (patch) | |
tree | 48e79a13dc012864045058f6ca3aadc3b9a767a8 /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker | |
parent | 0c8e025c3bd208e516f1c4247fdf3af7aebb2300 (diff) | |
download | gem5-99fb8f81407efa54008ddf443718e492f583b142.tar.xz |
stats: changes to due to recent set of patches
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker')
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini | 37 | ||||
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 1 |
2 files changed, 26 insertions, 12 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 78a71faf3..c26f32538 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -191,6 +192,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.checker.dtb [system.cpu.checker.dstage2_mmu.stage2_tlb] @@ -208,7 +210,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[9] [system.cpu.checker.dtb] type=ArmTLB @@ -225,7 +226,7 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[7] +port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.isa] type=ArmISA @@ -254,6 +255,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.checker.istage2_mmu] @@ -261,6 +263,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.checker.itb [system.cpu.checker.istage2_mmu.stage2_tlb] @@ -278,7 +281,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[8] [system.cpu.checker.itb] type=ArmTLB @@ -295,7 +297,7 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[6] +port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer @@ -307,6 +309,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -341,6 +344,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -358,7 +362,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -690,6 +693,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -750,6 +754,7 @@ id_mmfr3=34611729 id_pfr0=49 id_pfr1=4113 midr=1091551472 +pmu=Null system=system [system.cpu.istage2_mmu] @@ -757,6 +762,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -774,7 +780,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -799,6 +804,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -832,13 +838,16 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -848,6 +857,7 @@ eventq_index=0 type=LiveProcess cmd=hello cwd= +drivers= egid=100 env= errout=cerr @@ -856,6 +866,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello gid=100 input=cin +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -885,11 +896,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side @@ -920,7 +934,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -929,6 +943,7 @@ clk_domain=system.clk_domain conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 +device_size=536870912 devices_per_rank=8 dll=true eventq_index=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index eb7b98cb0..086544e33 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -773,7 +773,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 22770 # The number of ROB reads system.cpu.rob.rob_writes 21679 # The number of ROB writes system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself |