diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
commit | 1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch) | |
tree | dd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker | |
parent | 8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff) | |
download | gem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz |
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker')
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini | 44 |
1 files changed, 40 insertions, 4 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 6c1f65269..78a71faf3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -75,6 +75,7 @@ dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 +fetchQueueSize=32 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -98,7 +99,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 -numPhysCCRegs=0 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -128,7 +129,6 @@ switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 -wbDepth=1 wbWidth=8 workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -829,10 +829,11 @@ sequential_access=false size=2097152 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -862,6 +863,7 @@ ppid=99 simpoint=0 system=system uid=100 +useArchPT=false [system.cpu_clk_domain] type=SrcClockDomain @@ -880,10 +882,11 @@ sys_clk_domain=system.clk_domain transition_latency=100000000 [system.membus] -type=CoherentBus +type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -892,8 +895,33 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -902,6 +930,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -915,19 +944,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 |