regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 42 insertions, 33 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 773d3c5ec..49c4436f0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
 LSQDepCheckShift=4
-RASSize=16
 SQEntries=32
 SSITSize=1024
 activity=0
 backComSize=5
+branchPred=system.cpu.branchPred
 cachePorts=200
 checker=system.cpu.checker
-choiceCtrBits=2
-choicePredictorSize=8192
 clock=500
 commitToDecodeDelay=1
 commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
 fuPool=system.cpu.fuPool
 function_trace=false
 function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
 iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-instShiftAmt=2
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
-predType=tournament
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -126,9 +113,28 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
 [system.cpu.checker]
 type=O3Checker
 children=dtb isa itb tracer
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
@@ -598,7 +604,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index dbd9474aa..df6ac8e30 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  4 2013 21:17:24
-gem5 started Jan  4 2013 23:26:41
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:45
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 13372000 because target called exit()
+Exiting @ tick 13354000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 3f637a122..cbe7a8e01 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    13354000                       # Number of ticks simulated
 final_tick                                   13354000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46154                       # Simulator instruction rate (inst/s)
-host_op_rate                                    57584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              134203003                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242404                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  22763                       # Simulator instruction rate (inst/s)
+host_op_rate                                    28403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               66199618                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 285296                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17408                       # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits                         0                       # Nu
 system.physmem.readRowHitRate                   80.96                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        33747.46                       # Average gap between requests
+system.cpu.branchPred.lookups                    2501                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1795                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               485                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1976                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     702                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             35.526316                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     292                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 71                       # Number of incorrect RAS predictions.
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -276,14 +285,6 @@ system.cpu.itb.accesses                             0                       # DT
 system.cpu.numCycles                            26709                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2501                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1795                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                485                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1976                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      702                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      292                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  71                       # Number of incorrect RAS predictions.
 system.cpu.fetch.icacheStallCycles               6895                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          12010                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2501                       # Number of branches that fetch encountered