diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-04-08 11:01:45 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-04-08 11:01:45 -0500 |
| commit | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (patch) | |
| tree | 154e04d1dfb6159aaa5d553d238e2badb057acb3 /tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker | |
| parent | af27586fbc75480725fbef0564775fe5aa8cc8d8 (diff) | |
| download | gem5-1d61224a8ba60a2c8cb06e9877b7e548d47bb99a.tar.xz | |
stats: update stats for thermals, indirect BP
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini | 9 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 1151 |
2 files changed, 589 insertions, 571 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 0ad30e5d6..db680b227 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -147,11 +149,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.checker] type=O3Checker diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8c3704b45..b78b358b1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17170000 # Number of ticks simulated -final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17232500 # Number of ticks simulated +final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 9367 # Simulator instruction rate (inst/s) host_op_rate 10970 # Simulator op (including micro ops) rate (op/s) @@ -13,35 +13,35 @@ sim_insts 4592 # Nu sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted +system.physmem.num_reads::total 397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 90 # Per bank write bursts +system.physmem.perBankRdBursts::0 89 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts @@ -50,10 +50,10 @@ system.physmem.perBankRdBursts::5 32 # Pe system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 9 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 10 # Per bank write bursts system.physmem.perBankRdBursts::13 6 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts system.physmem.perBankRdBursts::15 6 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17097000 # Total gap between requests +system.physmem.totGap 17147000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) +system.physmem.readPktSize::6 397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,78 +187,82 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3045250 # Total ticks spent queuing -system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst +system.physmem.totQLat 3287250 # Total ticks spent queuing +system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.53 # Data bus utilization in percentage -system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.52 # Data bus utilization in percentage +system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43174.24 # Average gap between requests -system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined +system.physmem.avgGap 43191.44 # Average gap between requests +system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.108972 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states +system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) +system.physmem_0.averagePower 910.249171 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) -system.physmem_1.averagePower 807.028896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states +system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) +system.physmem_1.averagePower 808.014211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2537 # Number of BP lookups -system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups -system.cpu.branchPred.BTBHits 814 # Number of BTB hits +system.cpu.branchPred.lookups 2837 # Number of BP lookups +system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups +system.cpu.branchPred.BTBHits 865 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -496,235 +500,236 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34341 # number of cpu cycles simulated +system.cpu.numCycles 34466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2063 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1962 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2037 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups +system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 42 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 40 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12413 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7975 # Type of FU issued -system.cpu.iq.rate 0.232230 # Inst issue rate -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 8103 # Type of FU issued +system.cpu.iq.rate 0.235101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2933 # number of memory reference insts executed -system.cpu.iew.exec_branches 1435 # Number of branches executed -system.cpu.iew.exec_stores 1197 # Number of stores executed -system.cpu.iew.exec_rate 0.224251 # Inst execution rate -system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3459 # num instructions producing a value -system.cpu.iew.wb_consumers 6763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2923 # number of memory reference insts executed +system.cpu.iew.exec_branches 1492 # Number of branches executed +system.cpu.iew.exec_stores 1151 # Number of stores executed +system.cpu.iew.exec_rate 0.226716 # Inst execution rate +system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3504 # num instructions producing a value +system.cpu.iew.wb_consumers 6831 # num instructions consuming a value +system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -770,103 +775,103 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21787 # The number of ROB reads -system.cpu.rob.rob_writes 20281 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22311 # The number of ROB reads +system.cpu.rob.rob_writes 21303 # The number of ROB writes +system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7637 # number of integer regfile reads -system.cpu.int_regfile_writes 4176 # number of integer regfile writes +system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7659 # number of integer regfile reads +system.cpu.int_regfile_writes 4270 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27387 # number of cc regfile reads -system.cpu.cc_regfile_writes 3201 # number of cc regfile writes -system.cpu.misc_regfile_reads 3057 # number of misc regfile reads +system.cpu.cc_regfile_reads 27801 # number of cc regfile reads +system.cpu.cc_regfile_writes 3276 # number of cc regfile writes +system.cpu.misc_regfile_reads 3018 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2032 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2032 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2032 # number of overall hits -system.cpu.dcache.overall_hits::total 2032 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 181 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits +system.cpu.dcache.overall_hits::total 2074 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses +system.cpu.dcache.overall_misses::total 499 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.111936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.111936 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -875,16 +880,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -893,210 +898,214 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4235 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits -system.cpu.icache.overall_hits::total 1585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses -system.cpu.icache.overall_misses::total 386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4216 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses +system.cpu.icache.overall_misses::total 384 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 21 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 38 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.cpu.l2cache.overall_misses::total 401 # number of overall misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.800000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.800000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,119 +1114,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 354 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 396 # Request fanout histogram +system.membus.snoop_fanout::samples 397 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |