stats: updates due to recent chagnesets

3 files changed, 28 insertions, 11 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 76e4b0b8e..ceb6c35e9 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -24,6 +24,7 @@ mem_mode=timing
 mem_ranges=
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
 readfile=
 symbolfile=
@@ -166,7 +167,7 @@ eventq_index=0
 exitOnError=false
 function_trace=false
 function_trace_start=0
-interrupts=Null
+interrupts=
 isa=system.cpu.checker.isa
 istage2_mmu=system.cpu.checker.istage2_mmu
 itb=system.cpu.checker.itb
@@ -229,6 +230,7 @@ port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.checker.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -308,6 +310,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -324,6 +327,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -691,6 +695,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -707,6 +712,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -726,6 +732,7 @@ eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+decoderFlavour=Generic
 eventq_index=0
 fpsid=1090793632
 id_aa64afr0_el1=0
@@ -801,6 +808,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -817,6 +825,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -832,12 +841,13 @@ size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -845,6 +855,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 800acea54..8119abd2f 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 14 2015 23:30:05
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Nov 15 2015 15:24:37
+gem5 started Nov 15 2015 15:29:13
+gem5 executing on ribera.cs.wisc.edu, pid 11155
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 17163000 because target called exit()
+Exiting @ tick 17170000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 0fdcdba71..8297b21bd 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17170000                       # Number of ticks simulated
 final_tick                                   17170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54905                       # Simulator instruction rate (inst/s)
-host_op_rate                                    64292                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              205230571                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313448                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  30630                       # Simulator instruction rate (inst/s)
+host_op_rate                                    35868                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              114456188                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308252                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts