diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/arm/linux/o3-timing | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 485 |
1 files changed, 262 insertions, 223 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index b2921c80f..41f6b039e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17056000 # Number of ticks simulated -final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16955000 # Number of ticks simulated +final_tick 16955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53685 # Simulator instruction rate (inst/s) -host_op_rate 66982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 199380443 # Simulator tick rate (ticks/s) -host_mem_usage 308976 # Number of bytes of host memory used +host_inst_rate 52426 # Simulator instruction rate (inst/s) +host_op_rate 65410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193552438 # Simulator tick rate (ticks/s) +host_mem_usage 308400 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17280 # Nu system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1019168387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460513123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1479681510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1019168387 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1019168387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460513123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479681510 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 392 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16998500 # Total gap between requests +system.physmem.totGap 16897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,44 +186,48 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation -system.physmem.totQLat 4223500 # Total ticks spent queuing -system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 392.258065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 255.879233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.156911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.97% 20.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.90% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 72.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3795000 # Total ticks spent queuing +system.physmem.totMemAccLat 11145000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5431250 # Total ticks spent accessing banks -system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9681.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28431.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1479.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1479.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.56 # Data bus utilization in percentage +system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43363.52 # Average gap between requests +system.physmem.avgGap 43105.87 # Average gap between requests system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1467166979 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15324750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1475906812 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -235,9 +239,9 @@ system.membus.tot_pkt_size::total 25024 # Cu system.membus.data_through_bus 25024 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 3650250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2481 # Number of BP lookups system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted @@ -333,39 +337,39 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 34113 # number of cpu cycles simulated +system.cpu.numCycles 33911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6937 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2582 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.136583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.551452 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10625 80.18% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.71% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.71% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.68% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.03% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.09% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 9.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13252 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073162 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2857 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2426 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing @@ -374,9 +378,9 @@ system.cpu.decode.BranchMispred 159 # Nu system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7215 # Number of cycles rename is idle system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2286 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2227 # Number of cycles rename is running system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename @@ -403,23 +407,23 @@ system.cpu.iq.iqSquashedInstsIssued 113 # Nu system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673181 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.378149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9672 72.99% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.93% 82.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 814 6.14% 89.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 543 4.10% 93.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 259 1.95% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.94% 99.49% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13252 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available @@ -489,10 +493,10 @@ system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.261513 # Inst issue rate +system.cpu.iq.rate 0.263071 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31395 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -525,43 +529,43 @@ system.cpu.iew.memOrderViolationEvents 21 # Nu system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8524 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3299 # number of memory reference insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.249846 # Inst execution rate +system.cpu.iew.exec_rate 0.251364 # Inst execution rate system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8068 # cumulative count of insts written-back system.cpu.iew.wb_producers 3883 # num instructions producing a value -system.cpu.iew.wb_consumers 7788 # num instructions consuming a value +system.cpu.iew.wb_consumers 7789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back +system.cpu.iew.wb_rate 0.237917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498524 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297365 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1070 8.70% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 401 3.26% 93.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.43% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.28% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12301 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -572,25 +576,60 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5729 # Class of committed instruction system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23225 # The number of ROB reads +system.cpu.rob.rob_reads 23248 # The number of ROB reads system.cpu.rob.rob_writes 23415 # The number of ROB writes -system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20659 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39210 # number of integer regfile reads +system.cpu.cpi 7.386408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.386408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.135384 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.135384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39214 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1645768210 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -605,22 +644,22 @@ system.cpu.toL2Bus.data_through_bus 27904 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 480250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.354343 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.354343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071950 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses system.cpu.icache.tags.data_accesses 4184 # Number of data accesses @@ -636,12 +675,12 @@ system.cpu.icache.demand_misses::cpu.inst 363 # n system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses @@ -654,12 +693,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67991.735537 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67991.735537 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67991.735537 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67991.735537 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -680,39 +719,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 290 system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19694750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19694750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19694750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19694750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67912.931034 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67912.931034 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67912.931034 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.664460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.724086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.940374 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005666 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses @@ -736,17 +775,17 @@ system.cpu.l2cache.demand_misses::total 397 # nu system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 397 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19198250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6669000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 25867250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19198250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28869250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19198250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28869250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses) @@ -769,17 +808,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908467 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71104.629630 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77546.511628 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72660.814607 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72718.513854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71104.629630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76149.606299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72718.513854 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -805,17 +844,17 @@ system.cpu.l2cache.demand_mshr_misses::total 392 system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15805250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5377000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21182250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15805250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23680750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15805250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23680750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses @@ -827,39 +866,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58537.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66382.716049 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60348.290598 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58537.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64553.278689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60410.076531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.119879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.404110 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.119879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021270 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021270 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5932 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits @@ -876,22 +915,22 @@ system.cpu.dcache.demand_misses::cpu.data 496 # n system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses system.cpu.dcache.overall_misses::total 496 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11163493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11163493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31560493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31560493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31560493 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses @@ -902,22 +941,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59066.100529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59066.100529 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63630.026210 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63630.026210 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -944,14 +983,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6979005 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6979005 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10023005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10023005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -960,14 +999,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65839.669811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65839.669811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68183.707483 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68183.707483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |