diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick/se/00.hello/ref/arm/linux/o3-timing | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 660 |
1 files changed, 333 insertions, 327 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index c7177147a..8015f8322 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17777000 # Number of ticks simulated -final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17778000 # Number of ticks simulated +final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63242 # Simulator instruction rate (inst/s) -host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244740900 # Simulator tick rate (ticks/s) -host_mem_usage 307828 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58925 # Simulator instruction rate (inst/s) +host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228057572 # Simulator tick rate (ticks/s) +host_mem_usage 310616 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17763500 # Total gap between requests +system.physmem.totGap 17764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3130500 # Total ticks spent queuing -system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3121500 # Total ticks spent queuing +system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.45 # Data bus utilization in percentage @@ -224,35 +224,35 @@ system.physmem.readRowHits 340 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43644.96 # Average gap between requests +system.physmem.avgGap 43647.42 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.346375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states +system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.276555 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.767883 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states +system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.747987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2336 # Number of BP lookups system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35555 # number of cpu cycles simulated +system.cpu.numCycles 35557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5038 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5040 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4094 # Number of cycles rename is running +system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4096 # Number of cycles rename is running system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7146 # Type of FU issued -system.cpu.iq.rate 0.200984 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7148 # Type of FU issued +system.cpu.iq.rate 0.201029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed @@ -561,9 +561,9 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -572,7 +572,7 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -580,35 +580,35 @@ system.cpu.iew.exec_nop 14 # nu system.cpu.iew.exec_refs 2427 # number of memory reference insts executed system.cpu.iew.exec_branches 1272 # Number of branches executed system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189622 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2975 # num instructions producing a value -system.cpu.iew.wb_consumers 5372 # num instructions consuming a value +system.cpu.iew.exec_rate 0.189667 # Inst execution rate +system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6569 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2977 # num instructions producing a value +system.cpu.iew.wb_consumers 5378 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22320 # The number of ROB reads -system.cpu.rob.rob_writes 16439 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22343 # The number of ROB reads +system.cpu.rob.rob_writes 16451 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6718 # number of integer regfile reads -system.cpu.int_regfile_writes 3745 # number of integer regfile writes +system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6720 # number of integer regfile reads +system.cpu.int_regfile_writes 3747 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23959 # number of cc regfile reads +system.cpu.cc_regfile_reads 23965 # number of cc regfile reads system.cpu.cc_regfile_writes 2898 # number of cc regfile writes system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -709,16 +709,16 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -741,16 +741,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,14 +777,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -793,71 +793,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits -system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7943 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits +system.cpu.icache.overall_hits::total 3460 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296 system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -947,16 +947,16 @@ system.cpu.l2cache.overall_misses::cpu.data 113 # system.cpu.l2cache.overall_misses::total 386 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) @@ -983,16 +983,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,17 +1030,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1060,18 +1060,24 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution @@ -1087,15 +1093,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) @@ -1122,9 +1128,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |