diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/quick/se/00.hello/ref/arm/linux/o3-timing | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 1247 |
1 files changed, 624 insertions, 623 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4a87577c2..adfd7b504 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16786000 # Number of ticks simulated -final_tick 16786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16223000 # Number of ticks simulated +final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42967 # Simulator instruction rate (inst/s) -host_op_rate 53611 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157060125 # Simulator tick rate (ticks/s) -host_mem_usage 258920 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 35590 # Simulator instruction rate (inst/s) +host_op_rate 41676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125719954 # Simulator tick rate (ticks/s) +host_mem_usage 252016 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated +sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 392 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029429286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 465149529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1494578816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029429286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029429286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 465149529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1494578816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 392 # Number of read requests accepted +system.physmem.num_reads::total 397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::0 90 # Per bank write bursts system.physmem.perBankRdBursts::1 46 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 42 # Per bank write bursts -system.physmem.perBankRdBursts::4 17 # Per bank write bursts -system.physmem.perBankRdBursts::5 33 # Per bank write bursts +system.physmem.perBankRdBursts::3 43 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16721500 # Total gap between requests +system.physmem.totGap 16156000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 392 # Read request sizes (log2) +system.physmem.readPktSize::6 397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,72 +186,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.387097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.062800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.835382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 45.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.90% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 72.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 8.06% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 87.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 12.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3300000 # Total ticks spent queuing -system.physmem.totMemAccLat 10650000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8418.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2970000 # Total ticks spent queuing +system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27168.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1494.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1494.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage -system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.24 # Data bus utilization in percentage +system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42656.89 # Average gap between requests -system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 40695.21 # Average gap between requests +system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1494578816 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 350 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.throughput 1566171485 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 784 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25088 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 479500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3655500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2517 # Number of BP lookups -system.cpu.branchPred.condPredicted 1805 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 714 # Number of BTB hits +system.cpu.branchPred.lookups 2638 # Number of BP lookups +system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.664336 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 294 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,489 +336,491 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 33573 # number of cpu cycles simulated +system.cpu.numCycles 32447 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1008 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2659 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2378 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.162808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.572483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10430 79.69% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.73% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.55% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.82% 84.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 231 1.76% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 269 2.06% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 93 0.71% 89.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.11% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1254 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.074971 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359604 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2688 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 31 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 385 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13358 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 539 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7139 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 151 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2277 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2296 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 195 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 12625 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57590 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 47 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6952 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 329 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1583 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11316 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8961 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 149 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14803 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.684621 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.402607 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2145 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9594 73.30% 73.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1210 9.24% 82.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 823 6.29% 88.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 494 3.77% 92.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 3.66% 96.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 298 2.28% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 1.00% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.37% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.71% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 62.44% 65.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 34.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5369 59.92% 59.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2357 26.30% 86.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8961 # Type of FU issued -system.cpu.iq.rate 0.266911 # Inst issue rate -system.cpu.iq.fu_busy_cnt 221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31345 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16624 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8077 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9162 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 8358 # Type of FU issued +system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.fu_busy_cnt 169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1626 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 645 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11366 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 115 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2826 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1583 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 266 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 376 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 393 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3332 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed -system.cpu.iew.exec_stores 1172 # Number of stores executed -system.cpu.iew.exec_rate 0.255205 # Inst execution rate -system.cpu.iew.wb_sent 8256 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8093 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3919 # num instructions producing a value -system.cpu.iew.wb_consumers 8062 # num instructions consuming a value +system.cpu.iew.exec_nop 11 # number of nop insts executed +system.cpu.iew.exec_refs 3148 # number of memory reference insts executed +system.cpu.iew.exec_branches 1457 # Number of branches executed +system.cpu.iew.exec_stores 1240 # Number of stores executed +system.cpu.iew.exec_rate 0.248498 # Inst execution rate +system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7601 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3572 # num instructions producing a value +system.cpu.iew.wb_consumers 6998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.241057 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.486108 # average fanout of values written-back +system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5642 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.472651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.325156 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9924 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 978 8.07% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 402 3.32% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.85% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 175 1.44% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.75% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.41% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.27% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 123 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2138 # Number of memory references committed -system.cpu.commit.loads 1200 # Number of loads committed +system.cpu.commit.refs 1965 # Number of memory references committed +system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.branches 1007 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4976 # Number of committed integer instructions. +system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3584 62.56% 62.56% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 62.63% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.05% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1200 20.95% 83.63% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 938 16.37% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5729 # Class of committed instruction -system.cpu.commit.bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 5377 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23212 # The number of ROB reads -system.cpu.rob.rob_writes 23723 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22692 # The number of ROB reads +system.cpu.rob.rob_writes 21719 # The number of ROB writes +system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.312786 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.312786 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39407 # number of integer regfile reads -system.cpu.int_regfile_writes 7992 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 3253 # number of misc regfile reads +system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7944 # number of integer regfile reads +system.cpu.int_regfile_writes 4420 # number of integer regfile writes +system.cpu.fp_regfile_reads 31 # number of floating regfile reads +system.cpu.cc_regfile_reads 28734 # number of cc regfile reads +system.cpu.cc_regfile_writes 3302 # number of cc regfile writes +system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1662337662 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 394 # Transaction distribution +system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 870 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 480500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 229495 # Layer occupancy (ticks) +system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 148.488883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1601 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.520690 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 148.488883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.141113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits -system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses -system.cpu.icache.overall_misses::total 367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23960000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23960000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23960000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23960000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23960000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65286.103542 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65286.103542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65286.103542 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4430 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits +system.cpu.icache.overall_hits::total 1666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses +system.cpu.icache.overall_misses::total 402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.914747 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.940767 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.914747 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69196.296296 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78085.294118 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71324.647887 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74017.857143 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74017.857143 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71609.571788 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69196.296296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76740.157480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71609.571788 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,148 +835,148 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15291000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5345250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20636250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2596250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2596250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15291000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7941500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23232500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15291000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7941500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23232500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903226 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56633.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65094.262295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59266.581633 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.019573 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.438356 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.019573 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021245 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5964 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5964 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1782 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # 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number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 507 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 507 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 507 # number of overall misses -system.cpu.dcache.overall_misses::total 507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20684250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20684250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32297743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32297743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32297743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2885 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2885 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2885 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2885 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175737 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175737 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175737 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175737 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61123.647368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61123.647368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65250 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65250 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63703.635108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63703.635108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -984,30 +985,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6871755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3151750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10023505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10023505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050953 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65445.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75041.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68187.108844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68187.108844 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |