diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/quick/se/00.hello/ref/arm/linux/o3-timing | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 934 |
1 files changed, 467 insertions, 467 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 69573f93c..a58641eea 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17911000 # Number of ticks simulated -final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17788000 # Number of ticks simulated +final_tick 17788000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35404 # Simulator instruction rate (inst/s) -host_op_rate 41460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138087840 # Simulator tick rate (ticks/s) -host_mem_usage 236512 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 23007 # Simulator instruction rate (inst/s) +host_op_rate 26942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89104120 # Simulator tick rate (ticks/s) +host_mem_usage 300104 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975039352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388576568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97144142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1460760063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975039352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975039352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975039352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388576568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97144142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1460760063 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17897500 # Total gap between requests +system.physmem.totGap 17774500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -94,8 +94,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation -system.physmem.totQLat 3190492 # Total ticks spent queuing -system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 419.796610 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 279.431145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.786751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 13.56% 13.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 32.20% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 3111242 # Total ticks spent queuing +system.physmem.totMemAccLat 10742492 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7644.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26394.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1464.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1464.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.36 # Data bus utilization in percentage -system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.44 # Data bus utilization in percentage +system.physmem.busUtilRead 11.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 342 # Number of row buffer hits during reads +system.physmem.readRowHits 340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43974.20 # Average gap between requests -system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43671.99 # Average gap between requests +system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10829430 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) -system.physmem_0.averagePower 903.874941 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states +system.physmem_0.totalEnergy 14375115 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.162692 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 243500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15368000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.131217 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states +system.physmem_1.actBackEnergy 10100115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 639750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12751230 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.383231 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1024000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14302250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 476 # Number of BTB hits +system.cpu.branchPred.lookups 2340 # Number of BP lookups +system.cpu.branchPred.condPredicted 1388 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 507 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 52.744630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35823 # number of cpu cycles simulated +system.cpu.numCycles 35577 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 6129 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11284 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2340 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 732 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1057 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 3831 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14930 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.882251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.211921 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8724 58.43% 58.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2462 16.49% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 522 3.50% 78.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3222 21.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5024 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14930 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065773 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.317171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.decode.DecodedInsts 9870 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1626 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 964 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RunCycles 4098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 605 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8889 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 403 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40319 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9768 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3746 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1281 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8360 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3002 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7147 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3021 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7902 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.478701 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.863585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10739 71.93% 71.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1936 12.97% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1601 10.72% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 607 4.07% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,185 +466,185 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14930 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 420 29.23% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 467 32.50% 61.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4466 62.49% 62.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1084 15.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7136 # Type of FU issued -system.cpu.iq.rate 0.199202 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11372 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7147 # Type of FU issued +system.cpu.iq.rate 0.200888 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1437 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.201063 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30806 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11411 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6546 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8556 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 343 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 358 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8413 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1281 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1406 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2409 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1015 # Number of stores executed -system.cpu.iew.exec_rate 0.188036 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5387 # num instructions consuming a value +system.cpu.iew.exec_refs 2430 # number of memory reference insts executed +system.cpu.iew.exec_branches 1270 # Number of branches executed +system.cpu.iew.exec_stores 1024 # Number of stores executed +system.cpu.iew.exec_rate 0.189420 # Inst execution rate +system.cpu.iew.wb_sent 6605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2976 # num instructions producing a value +system.cpu.iew.wb_consumers 5371 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184445 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2578 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.373732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.023936 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11747 81.63% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1377 9.57% 91.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.20% 95.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 294 2.04% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.17% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 77 0.54% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.22% 99.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 14390 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4592 # Number of instructions committed +system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1965 # Number of memory references committed system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1007 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction @@ -653,104 +653,104 @@ system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Cl system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5377 # Class of committed instruction +system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22696 # The number of ROB reads -system.cpu.rob.rob_writes 16433 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.rob.rob_reads 22145 # The number of ROB reads +system.cpu.rob.rob_writes 16457 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20647 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4592 # Number of Instructions Simulated +system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.747605 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.747605 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129072 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129072 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 6713 # number of integer regfile reads -system.cpu.int_regfile_writes 3756 # number of integer regfile writes +system.cpu.int_regfile_writes 3745 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23929 # number of cc regfile reads -system.cpu.cc_regfile_writes 2892 # number of cc regfile writes -system.cpu.misc_regfile_reads 2595 # number of misc regfile reads +system.cpu.cc_regfile_reads 23953 # number of cc regfile reads +system.cpu.cc_regfile_writes 2889 # number of cc regfile writes +system.cpu.misc_regfile_reads 2609 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.188922 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.507042 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.188922 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164431 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4696 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4696 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1176 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1176 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits -system.cpu.dcache.overall_hits::total 1882 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1898 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1898 # number of overall hits +system.cpu.dcache.overall_hits::total 1898 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses -system.cpu.dcache.overall_misses::total 362 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses +system.cpu.dcache.overall_misses::total 357 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9257492 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9257492 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16534742 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16534742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16534742 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16534742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2255 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2255 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2255 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2255 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123696 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123696 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158315 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158315 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158315 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158315 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55768.024096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55768.024096 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46315.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46315.803922 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,16 +759,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -777,120 +777,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795755 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8163505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8163505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8163505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8163505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063415 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063415 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56821.127451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56821.127451 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.057531 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3467 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.752542 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.057531 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.265737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.265737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7977 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits -system.cpu.icache.overall_hits::total 3477 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 7955 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7955 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3467 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3467 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3467 # number of overall hits +system.cpu.icache.overall_hits::total 3467 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21749991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21749991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21749991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21749991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21749991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21749991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3830 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3830 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3830 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3830 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094778 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094778 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094778 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094778 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094778 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094778 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59917.330579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59917.330579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59917.330579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59917.330579 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8313 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 90 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.366667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18519493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18519493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18519493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18519493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18519493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18519493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077063 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077063 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077063 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62565.854730 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62565.854730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18653743 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18653743 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18653743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18653743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18653743 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18653743 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077285 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077285 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077285 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63019.402027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63019.402027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.519523 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.560599 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.350778 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.044062 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.165759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002749 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011753 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -943,17 +943,17 @@ system.cpu.l2cache.demand_misses::total 386 # nu system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses system.cpu.l2cache.overall_misses::total 386 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18219750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5781750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24001500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18354000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5568750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23922750 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18219750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8035500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26255250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18219750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8035500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26255250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7822500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18354000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7822500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26176500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) @@ -976,17 +976,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.879271 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67230.769231 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67093.373494 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67198.735955 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67814.766839 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67814.766839 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,20 +1018,20 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4617750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20611750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22614500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6620500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24256417 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses @@ -1046,20 +1046,20 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58801.470588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59201.923077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58890.714286 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59511.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56673.871495 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution @@ -1088,7 +1088,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 4 # system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 496999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) @@ -1111,9 +1111,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 508443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2142008 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |