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authorNilay Vaish <nilay@cs.wisc.edu>2015-11-16 05:08:57 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2015-11-16 05:08:57 -0600
commitde489e1997ee6c37aaf6e876e32622f6c648fe95 (patch)
tree40d4093453491b007167c971ebbb18c8ae0b77fa /tests/quick/se/00.hello/ref/arm/linux/o3-timing
parent08cec03f8ec3bc427700343a7bd7d216433f93fc (diff)
downloadgem5-de489e1997ee6c37aaf6e876e32622f6c648fe95.tar.xz
stats: updates due to recent chagnesets
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini18
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing/simout13
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt10
3 files changed, 29 insertions, 12 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index cc7bd2d63..9b45b3947 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -24,6 +24,7 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
readfile=
symbolfile=
@@ -154,6 +155,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@@ -170,6 +172,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
+writeback_clean=true
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -495,6 +498,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@@ -511,6 +515,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -530,6 +535,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -605,6 +611,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@@ -621,6 +628,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -661,12 +669,13 @@ size=1048576
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -674,6 +683,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index 8e08379a3..6e552ddd3 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,13 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 22 2015 10:58:25
-gem5 started Apr 22 2015 11:26:41
-gem5 executing on phenom
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Nov 15 2015 15:24:37
+gem5 started Nov 15 2015 15:25:11
+gem5 executing on ribera.cs.wisc.edu, pid 11031
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x4144ba0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 17911000 because target called exit()
+Exiting @ tick 18741000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 087d46b3f..ff1efaffe 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
sim_ticks 18741000 # Number of ticks simulated
final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59386 # Simulator instruction rate (inst/s)
-host_op_rate 69540 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 242288300 # Simulator tick rate (ticks/s)
-host_mem_usage 309720 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 9085 # Simulator instruction rate (inst/s)
+host_op_rate 10640 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37077299 # Simulator tick rate (ticks/s)
+host_mem_usage 304792 # Number of bytes of host memory used
+host_seconds 0.51 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts