stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

1 files changed, 96 insertions, 32 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 398374723..72322cbec 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 582910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   681582                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              341032781                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293692                       # Number of bytes of host memory used
+host_inst_rate                                 396323                       # Simulator instruction rate (inst/s)
+host_op_rate                                   463654                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              232084410                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298640                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5377                       # Number of ops (including micro ops) simulated
@@ -35,35 +35,15 @@ system.physmem.bw_write::total             1353868992                       # Wr
 system.physmem.bw_total::cpu.inst          6834663203                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3020597513                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9855260716                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
-system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
-system.membus.trans_dist::WriteReq                913                       # Transaction distribution
-system.membus.trans_dist::WriteResp               913                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
-system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.dtb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                         0                       # DTB hits
 system.cpu.checker.dtb.misses                       0                       # DTB misses
 system.cpu.checker.dtb.accesses                     0                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.itb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
@@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5390                       # Class of executed instruction
+system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
+system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
+system.membus.trans_dist::WriteReq                913                       # Transaction distribution
+system.membus.trans_dist::WriteResp               913                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
+system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------