stats: update stats for ARMv8 changes

3 files changed, 234 insertions, 19 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 1158c75dc..baee5cb0e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -18,6 +18,7 @@ eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=atomic
 mem_ranges=
 memories=system.physmem
@@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=checker dtb interrupts isa itb tracer workload
+children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
 checker=system.cpu.checker
 clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
 dtb=system.cpu.dtb
 eventq_index=0
 fastmem=false
@@ -55,6 +57,7 @@ function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
 isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -79,13 +82,14 @@ icache_port=system.membus.slave[1]
 
 [system.cpu.checker]
 type=DummyChecker
-children=dtb isa itb tracer
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=-1
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
+dstage2_mmu=system.cpu.checker.dstage2_mmu
 dtb=system.cpu.checker.dtb
 eventq_index=0
 exitOnError=false
@@ -93,6 +97,7 @@ function_trace=false
 function_trace_start=0
 interrupts=Null
 isa=system.cpu.checker.isa
+istage2_mmu=system.cpu.checker.istage2_mmu
 itb=system.cpu.checker.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -109,10 +114,34 @@ updateOnError=false
 warnOnlyOnLoadError=true
 workload=system.cpu.workload
 
+[system.cpu.checker.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+tlb=system.cpu.checker.dtb
+
+[system.cpu.checker.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
 [system.cpu.checker.dtb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.checker.dtb.walker
 
@@ -120,6 +149,7 @@ walker=system.cpu.checker.dtb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 
@@ -127,24 +157,59 @@ sys=system
 type=ArmISA
 eventq_index=0
 fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
 id_isar3=17899825
 id_isar4=268501314
 id_isar5=0
-id_mmfr0=3
+id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
-id_mmfr3=4027589137
+id_mmfr3=34611729
 id_pfr0=49
-id_pfr1=1
-midr=890224640
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.checker.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+tlb=system.cpu.checker.itb
+
+[system.cpu.checker.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.checker.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
 
 [system.cpu.checker.itb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.checker.itb.walker
 
@@ -152,6 +217,7 @@ walker=system.cpu.checker.itb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 
@@ -159,10 +225,35 @@ sys=system
 type=ExeTracer
 eventq_index=0
 
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[6]
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.dtb.walker
 
@@ -170,6 +261,7 @@ walker=system.cpu.dtb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -182,24 +274,60 @@ eventq_index=0
 type=ArmISA
 eventq_index=0
 fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
 id_isar0=34607377
 id_isar1=34677009
 id_isar2=555950401
 id_isar3=17899825
 id_isar4=268501314
 id_isar5=0
-id_mmfr0=3
+id_mmfr0=270536963
 id_mmfr1=0
 id_mmfr2=19070976
-id_mmfr3=4027589137
+id_mmfr3=34611729
 id_pfr0=49
-id_pfr1=1
-midr=890224640
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[5]
 
 [system.cpu.itb]
 type=ArmTLB
 children=walker
 eventq_index=0
+is_stage2=false
 size=64
 walker=system.cpu.itb.walker
 
@@ -207,6 +335,7 @@ walker=system.cpu.itb.walker
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
 eventq_index=0
+is_stage2=false
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -250,7 +379,7 @@ system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 7509c2dae..c5ba01efb 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,11 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 17:24:06
-gem5 started Jan 22 2014 17:30:32
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 17:06:13
 gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
+      0: system.cpu.checker.isa: ISA system set to: 0 0x4499a00
+      0: system.cpu.isa: ISA system set to: 0 0x4499a00
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
 Exiting @ tick 2870500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 4b1e74a91..a171618e9 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61907                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77238                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38693079                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237008                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 147367                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183813                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               92059834                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256900                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -39,6 +39,27 @@ system.membus.throughput                   9251001568                       # Th
 system.membus.data_through_bus                  26555                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
+system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -60,6 +81,27 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                         0                       # DTB hits
 system.cpu.checker.dtb.misses                       0                       # DTB misses
 system.cpu.checker.dtb.accesses                     0                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
+system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
@@ -85,6 +127,27 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -106,6 +169,27 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -138,7 +222,7 @@ system.cpu.num_func_calls                         203                       # nu
 system.cpu.num_conditional_control_insts          792                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         4976                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads               25195                       # number of times the integer registers were read
+system.cpu.num_int_register_reads               25360                       # number of times the integer registers were read
 system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written