CheckerCPU: Make some basic regression tests for CheckerCPU

Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.

4 files changed, 336 insertions, 0 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
new file mode 100644
index 000000000..305feda00
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -0,0 +1,188 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=checker dtb interrupts itb tracer workload
+checker=system.cpu.checker
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.checker]
+type=DummyChecker
+children=dtb itb tracer
+checker=Null
+clock=1
+cpu_id=-1
+defer_registration=false
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.checker.dtb
+function_trace=false
+function_trace_start=0
+interrupts=Null
+itb=system.cpu.checker.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+profile=0
+progress_interval=0
+system=system
+tracer=system.cpu.checker.tracer
+workload=system.cpu.workload
+
+[system.cpu.checker.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.checker.dtb.walker
+
+[system.cpu.checker.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+
+[system.cpu.checker.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.checker.itb.walker
+
+[system.cpu.checker.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+
+[system.cpu.checker.tracer]
+type=ExeTracer
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
new file mode 100755
index 000000000..ee81f724d
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -0,0 +1,11 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Mar  8 2012 09:03:12
+gem5 started Mar  8 2012 09:06:54
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Hello world!
+Exiting @ tick 2875500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
new file mode 100644
index 000000000..f9b36225f
--- /dev/null
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -0,0 +1,135 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000003                       # Number of seconds simulated
+sim_ticks                                     2875500                       # Number of ticks simulated
+final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  76819                       # Simulator instruction rate (inst/s)
+host_op_rate                                    95818                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47998674                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212240                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+sim_insts                                        4600                       # Number of instructions simulated
+sim_ops                                          5739                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  18452                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                     3648                       # Number of bytes written to this memory
+system.physmem.num_reads                         5771                       # Number of read requests responded to by this memory
+system.physmem.num_writes                         924                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     7979134064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                6416970962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                    1268648931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    9247782994                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
+system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
+system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
+system.cpu.checker.dtb.read_misses                  0                       # DTB read misses
+system.cpu.checker.dtb.write_hits                   0                       # DTB write hits
+system.cpu.checker.dtb.write_misses                 0                       # DTB write misses
+system.cpu.checker.dtb.flush_tlb                    0                       # Number of times complete TLB was flushed
+system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries                0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.dtb.prefetch_faults              0                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.dtb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses                0                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses               0                       # DTB write accesses
+system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
+system.cpu.checker.dtb.hits                         0                       # DTB hits
+system.cpu.checker.dtb.misses                       0                       # DTB misses
+system.cpu.checker.dtb.accesses                     0                       # DTB accesses
+system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
+system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
+system.cpu.checker.itb.read_hits                    0                       # DTB read hits
+system.cpu.checker.itb.read_misses                  0                       # DTB read misses
+system.cpu.checker.itb.write_hits                   0                       # DTB write hits
+system.cpu.checker.itb.write_misses                 0                       # DTB write misses
+system.cpu.checker.itb.flush_tlb                    0                       # Number of times complete TLB was flushed
+system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
+system.cpu.checker.itb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries                0                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
+system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
+system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
+system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
+system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
+system.cpu.checker.itb.inst_accesses                0                       # ITB inst accesses
+system.cpu.checker.itb.hits                         0                       # DTB hits
+system.cpu.checker.itb.misses                       0                       # DTB misses
+system.cpu.checker.itb.accesses                     0                       # DTB accesses
+system.cpu.workload.num_syscalls                   13                       # Number of system calls
+system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
+system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
+system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.numCycles                             5752                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                        4600                       # Number of instructions committed
+system.cpu.committedOps                          5739                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
+system.cpu.num_func_calls                         185                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts          793                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4985                       # number of integer instructions
+system.cpu.num_fp_insts                            16                       # number of float instructions
+system.cpu.num_int_register_reads               25237                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               5345                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
+system.cpu.num_mem_refs                          2139                       # number of memory refs
+system.cpu.num_load_insts                        1201                       # Number of load instructions
+system.cpu.num_store_insts                        938                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                       5752                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------