summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2014-05-09 18:58:50 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-05-09 18:58:50 -0400
commit57e5401d954d46fea45ca3eaafa8ae655659da39 (patch)
tree7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
parentaa329f4757639820f921bf4152c21e79da74c034 (diff)
downloadgem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt45
1 files changed, 40 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 584aefada..2a0a91e3f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 82560 # Simulator instruction rate (inst/s)
-host_op_rate 102991 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51587489 # Simulator tick rate (ticks/s)
-host_mem_usage 311624 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 770690 # Simulator instruction rate (inst/s)
+host_op_rate 959471 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 479615706 # Simulator tick rate (ticks/s)
+host_mem_usage 296608 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -147,5 +147,40 @@ system.cpu.num_busy_cycles 5742 # Nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction
+system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction
+system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction
+system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 5742 # Class of executed instruction
---------- End Simulation Statistics ----------