stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

1 files changed, 146 insertions, 144 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index ba11ac8e8..f26a07dcf 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    25969000                       # Number of ticks simulated
-final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    25815000                       # Number of ticks simulated
+final_tick                                   25815000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 376681                       # Simulator instruction rate (inst/s)
-host_op_rate                                   467447                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2137718143                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306356                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  85918                       # Simulator instruction rate (inst/s)
+host_op_rate                                   100276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              485659481                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277384                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
-sim_ops                                          5672                       # Number of ops (including micro ops) simulated
+sim_ops                                          5329                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   350                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            554507297                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            308059610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               862566907                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       554507297                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          554507297                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           554507297                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           308059610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              862566907                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                    862566907                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst            557815224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            309897347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               867712570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       557815224                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          557815224                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           557815224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           309897347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              867712570                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                    867712570                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 307                       # Transaction distribution
 system.membus.trans_dist::ReadResp                307                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
@@ -40,10 +40,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               22400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  22400                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              350000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3150000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.1                       # Layer utilization (%)
+system.membus.reqLayer0.occupancy              355000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3155000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -130,73 +130,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            51938                       # number of cpu cycles simulated
+system.cpu.numCycles                            51630                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4565                       # Number of instructions committed
-system.cpu.committedOps                          5672                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4976                       # Number of integer alu accesses
+system.cpu.committedOps                          5329                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4624                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         203                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          792                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4976                       # number of integer instructions
+system.cpu.num_conditional_control_insts          722                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4624                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads               28821                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5334                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7573                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               2728                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2138                       # number of memory refs
-system.cpu.num_load_insts                        1200                       # Number of load instructions
+system.cpu.num_cc_register_reads                19184                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes                2432                       # number of times the CC registers were written
+system.cpu.num_mem_refs                          1965                       # number of memory refs
+system.cpu.num_load_insts                        1027                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      51938                       # Number of busy cycles
+system.cpu.num_busy_cycles                      51630                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                              1007                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                      3597     62.64%     62.64% # Class of executed instruction
-system.cpu.op_class::IntMult                        4      0.07%     62.71% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     62.71% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  3      0.05%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     62.77% # Class of executed instruction
-system.cpu.op_class::MemRead                     1200     20.90%     83.66% # Class of executed instruction
-system.cpu.op_class::MemWrite                     938     16.34%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                      3418     63.41%     63.41% # Class of executed instruction
+system.cpu.op_class::IntMult                        4      0.07%     63.49% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.54% # Class of executed instruction
+system.cpu.op_class::MemRead                     1027     19.05%     82.60% # Class of executed instruction
+system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                       5742                       # Class of executed instruction
+system.cpu.op_class::total                       5390                       # Class of executed instruction
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           114.614391                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           114.428477                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4364                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               241                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             18.107884                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   114.614391                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.055964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   114.428477                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.055873                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.055873                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          240                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
@@ -215,12 +217,12 @@ system.cpu.icache.demand_misses::cpu.inst          241                       # n
 system.cpu.icache.demand_misses::total            241                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          241                       # number of overall misses
 system.cpu.icache.overall_misses::total           241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12583000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12583000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12583000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12583000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12583000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12583000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12588000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12588000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12588000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12588000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12588000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12588000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         4605                       # number of demand (read+write) accesses
@@ -233,12 +235,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.052334
 system.cpu.icache.demand_miss_rate::total     0.052334                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052334                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.052334                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52211.618257                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52232.365145                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52232.365145                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -253,36 +255,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          241
 system.cpu.icache.demand_mshr_misses::total          241                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          241                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          241                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12101000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12101000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12106000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12106000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12106000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12106000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052334                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.052334                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052334                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.052334                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          154.071129                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          153.844437                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.889758                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    48.181371                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003231                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004702                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   105.714938                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    48.129500                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003226                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001469                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004695                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
@@ -309,17 +311,17 @@ system.cpu.l2cache.demand_misses::total           350                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          125                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          350                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11700000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11705000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4264000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     15964000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15969000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2236000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2236000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     11700000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11705000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      6500000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     18200000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     11700000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18205000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11705000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      6500000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     18200000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18205000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          241                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           98                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          339                       # number of ReadReq accesses(hits+misses)
@@ -342,17 +344,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.916230                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.933610                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.886525                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916230                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -407,32 +409,32 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.000387                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1940                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            82.900177                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1786                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.758865                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.666667                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.000387                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020264                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.900177                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020239                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020239                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4303                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4303                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              3995                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             3995                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          894                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             894                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            870                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1918                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1918                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1918                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1918                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1764                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1764                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1764                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1764                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           98                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            98                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
@@ -449,26 +451,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7083000
 system.cpu.dcache.demand_miss_latency::total      7083000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7083000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7083000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1146                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1146                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          992                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2059                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2059                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2059                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2059                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085515                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.085515                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098790                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098790                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.068480                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.068480                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.068480                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.068480                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074016                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074016                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
@@ -501,14 +503,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6801000
 system.cpu.dcache.demand_mshr_miss_latency::total      6801000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.085515                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.085515                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098790                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098790                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.068480                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.068480                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.068480                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.068480                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074016                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -518,7 +520,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               941430167                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput               947046291                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution