diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/00.hello/ref/arm/linux/simple-timing | |
parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing')
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt | 203 |
1 files changed, 107 insertions, 96 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index eccfa92c7..85d747802 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25816500 # Number of ticks simulated final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77759 # Simulator instruction rate (inst/s) -host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439383785 # Simulator tick rate (ticks/s) -host_mem_usage 301384 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 428411 # Simulator instruction rate (inst/s) +host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2416370273 # Simulator tick rate (ticks/s) +host_mem_usage 308620 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -384,100 +384,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency @@ -492,55 +498,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) @@ -548,27 +559,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) |