stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 83487a6ff..facfa8248 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 286813                       # Simulator instruction rate (inst/s)
-host_op_rate                                   333728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1769783602                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267436                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 441317                       # Simulator instruction rate (inst/s)
+host_op_rate                                   514292                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2726097982                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267744                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -284,8 +284,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           98                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
@@ -318,7 +316,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           114.043293                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4365                       # Total number of references to valid blocks.
@@ -376,8 +373,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          241                       # number of ReadReq MSHR misses
@@ -404,7 +399,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585
 system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          153.328645                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 32                       # Total number of references to valid blocks.
@@ -498,8 +492,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          225                       # number of ReadCleanReq MSHR misses
@@ -548,7 +540,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          383                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests           32                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            1                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.