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authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
commitb63631536d974f31cf99ee280271dc0f7b4c746f (patch)
treeff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/quick/se/00.hello/ref/arm/linux/simple-timing
parent646c4a23ca44aab5468c896034288151c89be782 (diff)
downloadgem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt82
1 files changed, 41 insertions, 41 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 7a58b161f..13e2763d6 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu
sim_ticks 25969000 # Number of ticks simulated
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 220478 # Simulator instruction rate (inst/s)
-host_op_rate 273604 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1251201624 # Simulator tick rate (ticks/s)
-host_mem_usage 241012 # Number of bytes of host memory used
+host_inst_rate 229244 # Simulator instruction rate (inst/s)
+host_op_rate 284503 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1301168988 # Simulator tick rate (ticks/s)
+host_mem_usage 238660 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated
sim_ops 5672 # Number of ops (including micro ops) simulated
@@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 307 # Tr
system.membus.trans_dist::ReadResp 307 # Transaction distribution
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 700 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 22400 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
@@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 51938 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 1 # number of replacements
-system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 1 # number of replacements
+system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits
@@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
@@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
@@ -424,12 +424,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 339 # Tr
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)