ARM: Update stats for CBNZ fix.

3 files changed, 22 insertions, 20 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 1d87891a2..50ec8fd07 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -26,7 +26,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +80,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=ArmTLB
@@ -93,11 +93,11 @@ type=ArmTableWalker
 max_backoff=100000
 min_backoff=0
 sys=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -118,7 +118,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
@@ -134,11 +134,11 @@ type=ArmTableWalker
 max_backoff=100000
 min_backoff=0
 sys=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -158,8 +158,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -169,7 +169,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -201,7 +202,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=PhysicalMemory
@@ -211,5 +213,5 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index 378a682d4..25b5aeda6 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:36:11
+gem5 compiled Mar  9 2012 10:15:20
+gem5 started Mar  9 2012 10:17:15
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index a93efeca8..4b008ff5c 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    26361000                       # Number of ticks simulated
 final_tick                                   26361000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 456104                       # Simulator instruction rate (inst/s)
-host_op_rate                                   565540                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2619225899                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220184                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  29458                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36586                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              169706423                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223936                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        4574                       # Number of instructions simulated
 sim_ops                                          5682                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       22400                       # Number of bytes read from this memory