Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index ae539a028..059498d9f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    27316000                       # Number of ticks simulated
-final_tick                                   27316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000026                       # Number of seconds simulated
+sim_ticks                                    25969000                       # Number of ticks simulated
+final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  78983                       # Simulator instruction rate (inst/s)
-host_op_rate                                    98109                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              472376751                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225996                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 147661                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              839095918                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231680                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5672                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   350                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            527163567                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            292868648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               820032216                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       527163567                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          527163567                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           527163567                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           292868648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              820032216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            554507297                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            308059610                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               862566907                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       554507297                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          554507297                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           554507297                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           308059610                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              862566907                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            54632                       # number of cpu cycles simulated
+system.cpu.numCycles                            51938                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4565                       # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs                          2138                       # nu
 system.cpu.num_load_insts                        1200                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      54632                       # Number of busy cycles
+system.cpu.num_busy_cycles                      51938                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                114.832264                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                114.614391                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     4364                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.107884                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     114.832264                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.056070                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.056070                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     114.614391                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.055964                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         4364                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4364                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4364                       # number of demand (read+write) hits
@@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst          241                       # n
 system.cpu.icache.demand_misses::total            241                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          241                       # number of overall misses
 system.cpu.icache.overall_misses::total           241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12824000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12824000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12824000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12824000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12583000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12583000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12583000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12583000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12583000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12583000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         4605                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         4605                       # number of demand (read+write) accesses
@@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.052334
 system.cpu.icache.demand_miss_rate::total     0.052334                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052334                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.052334                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53211.618257                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52211.618257                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52211.618257                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257
 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 83.122861                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 83.000387                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1940                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.758865                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      83.122861                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020294                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020294                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      83.000387                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020264                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
@@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data          141                       # n
 system.cpu.dcache.demand_misses::total            141                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          141                       # number of overall misses
 system.cpu.dcache.overall_misses::total           141                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4816000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4816000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2408000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2408000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7224000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7224000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7224000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7224000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4718000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4718000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2365000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2365000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7083000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7083000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7083000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7083000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1146                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1146                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.068480
 system.cpu.dcache.demand_miss_rate::total     0.068480                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.068480                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.068480                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 51234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 51234.042553                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 50234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 50234.042553                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               154.336658                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               154.071129                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                      32                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    106.089659                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     48.246999                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003238                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001472                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004710                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    105.889758                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     48.181371                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003231                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004702                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits