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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-30 12:24:19 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-30 12:24:19 -0500 |
commit | 66941163e50abceaa86c5eb6a18de6bbc2ec4ef8 (patch) | |
tree | 695a23cc938e997e1bc5f318576aa84c186a9aab /tests/quick/se/00.hello/ref/arm/linux/simple-timing | |
parent | a60a93eb051d49b86e33ed8add06f65fcdb37604 (diff) | |
download | gem5-66941163e50abceaa86c5eb6a18de6bbc2ec4ef8.tar.xz |
stats: updates due to recent changes.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing')
-rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 5fb17fcaa..0e18c01bd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -89,7 +89,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -100,7 +100,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -157,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -166,7 +165,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -177,7 +176,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -268,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -277,7 +275,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -288,7 +286,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] |