diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/se/00.hello/ref/arm/linux/simple-timing | |
parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing')
3 files changed, 36 insertions, 36 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 89402c0d8..e19a07626 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index d4a066c4f..16fea9a8f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:26 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:19:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26351000 because target called exit() +Exiting @ tick 27316000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index bac15b503..0ed449cb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26351000 # Number of ticks simulated -final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27316000 # Number of ticks simulated +final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50718 # Simulator instruction rate (inst/s) -host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292657577 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used +host_inst_rate 53670 # Simulator instruction rate (inst/s) +host_op_rate 66671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321019881 # Simulator tick rate (ticks/s) +host_mem_usage 231588 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52702 # number of cpu cycles simulated +system.cpu.numCycles 54632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52702 # Number of busy cycles +system.cpu.num_busy_cycles 54632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits |