diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-04-08 11:01:45 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-04-08 11:01:45 -0500 |
| commit | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (patch) | |
| tree | 154e04d1dfb6159aaa5d553d238e2badb057acb3 /tests/quick/se/00.hello/ref/arm/linux | |
| parent | af27586fbc75480725fbef0564775fe5aa8cc8d8 (diff) | |
| download | gem5-1d61224a8ba60a2c8cb06e9877b7e548d47bb99a.tar.xz | |
stats: update stats for thermals, indirect BP
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux')
9 files changed, 1498 insertions, 1412 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index 98b98ce6b..0858c144d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -122,11 +124,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -137,7 +146,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -598,7 +606,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -711,7 +718,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -746,6 +752,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -811,6 +818,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 586c80689..02dbcdc04 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29949500 # Number of ticks simulated -final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29977500 # Number of ticks simulated +final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 167534 # Simulator instruction rate (inst/s) host_op_rate 196036 # Simulator op (including micro ops) rate (op/s) @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29858000 # Total gap between requests +system.physmem.totGap 29886000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2201000 # Total ticks spent queuing -system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2113500 # Total ticks spent queuing +system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.03 # Data bus utilization in percentage -system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.02 # Data bus utilization in percentage +system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70921.62 # Average gap between requests +system.physmem.avgGap 70988.12 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -241,24 +241,28 @@ system.physmem_1.preEnergy 70125 # En system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ) -system.physmem_1.averagePower 784.282403 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states +system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.269066 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1912 # Number of BP lookups -system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups -system.cpu.branchPred.BTBHits 347 # Number of BTB hits +system.cpu.branchPred.lookups 1949 # Number of BP lookups +system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 316 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 125 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,44 +381,79 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59899 # number of cpu cycles simulated +system.cpu.numCycles 59955 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.007383 # CPI: cycles per instruction -system.cpu.ipc 0.076879 # IPC: instructions per cycle -system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.019544 # CPI: cycles per instruction +system.cpu.ipc 0.076808 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction +system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction +system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction +system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 5391 # Class of committed instruction +system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits -system.cpu.dcache.overall_hits::total 1893 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits +system.cpu.dcache.overall_hits::total 1894 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -423,42 +462,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,82 +522,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4806 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits -system.cpu.icache.overall_hits::total 1920 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses -system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4821 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits +system.cpu.icache.overall_hits::total 1926 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses +system.cpu.icache.overall_misses::total 323 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,62 +606,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 3 # number of writebacks -system.cpu.icache.writebacks::total 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 4 # number of writebacks +system.cpu.icache.writebacks::total 4 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses -system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits +system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses @@ -635,56 +674,56 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,76 +750,76 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) @@ -803,9 +842,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 0ad30e5d6..db680b227 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -147,11 +149,18 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 +useIndirect=true [system.cpu.checker] type=O3Checker diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8c3704b45..b78b358b1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17170000 # Number of ticks simulated -final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17232500 # Number of ticks simulated +final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 9367 # Simulator instruction rate (inst/s) host_op_rate 10970 # Simulator op (including micro ops) rate (op/s) @@ -13,35 +13,35 @@ sim_insts 4592 # Nu sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted +system.physmem.num_reads::total 397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 90 # Per bank write bursts +system.physmem.perBankRdBursts::0 89 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts @@ -50,10 +50,10 @@ system.physmem.perBankRdBursts::5 32 # Pe system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts +system.physmem.perBankRdBursts::9 9 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts +system.physmem.perBankRdBursts::12 10 # Per bank write bursts system.physmem.perBankRdBursts::13 6 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts system.physmem.perBankRdBursts::15 6 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17097000 # Total gap between requests +system.physmem.totGap 17147000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) +system.physmem.readPktSize::6 397 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,78 +187,82 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3045250 # Total ticks spent queuing -system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst +system.physmem.totQLat 3287250 # Total ticks spent queuing +system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.53 # Data bus utilization in percentage -system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.52 # Data bus utilization in percentage +system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43174.24 # Average gap between requests -system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined +system.physmem.avgGap 43191.44 # Average gap between requests +system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.108972 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states +system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) +system.physmem_0.averagePower 910.249171 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) -system.physmem_1.averagePower 807.028896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states +system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) +system.physmem_1.averagePower 808.014211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2537 # Number of BP lookups -system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups -system.cpu.branchPred.BTBHits 814 # Number of BTB hits +system.cpu.branchPred.lookups 2837 # Number of BP lookups +system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups +system.cpu.branchPred.BTBHits 865 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -496,235 +500,236 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34341 # number of cpu cycles simulated +system.cpu.numCycles 34466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2063 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1962 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2037 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups +system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 42 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 40 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12413 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7975 # Type of FU issued -system.cpu.iq.rate 0.232230 # Inst issue rate -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 8103 # Type of FU issued +system.cpu.iq.rate 0.235101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2933 # number of memory reference insts executed -system.cpu.iew.exec_branches 1435 # Number of branches executed -system.cpu.iew.exec_stores 1197 # Number of stores executed -system.cpu.iew.exec_rate 0.224251 # Inst execution rate -system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3459 # num instructions producing a value -system.cpu.iew.wb_consumers 6763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2923 # number of memory reference insts executed +system.cpu.iew.exec_branches 1492 # Number of branches executed +system.cpu.iew.exec_stores 1151 # Number of stores executed +system.cpu.iew.exec_rate 0.226716 # Inst execution rate +system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7439 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3504 # num instructions producing a value +system.cpu.iew.wb_consumers 6831 # num instructions consuming a value +system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -770,103 +775,103 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21787 # The number of ROB reads -system.cpu.rob.rob_writes 20281 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22311 # The number of ROB reads +system.cpu.rob.rob_writes 21303 # The number of ROB writes +system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7637 # number of integer regfile reads -system.cpu.int_regfile_writes 4176 # number of integer regfile writes +system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7659 # number of integer regfile reads +system.cpu.int_regfile_writes 4270 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27387 # number of cc regfile reads -system.cpu.cc_regfile_writes 3201 # number of cc regfile writes -system.cpu.misc_regfile_reads 3057 # number of misc regfile reads +system.cpu.cc_regfile_reads 27801 # number of cc regfile reads +system.cpu.cc_regfile_writes 3276 # number of cc regfile writes +system.cpu.misc_regfile_reads 3018 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2032 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2032 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2032 # number of overall hits -system.cpu.dcache.overall_hits::total 2032 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 181 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits +system.cpu.dcache.overall_hits::total 2074 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses +system.cpu.dcache.overall_misses::total 499 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2530 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2530 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2530 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2530 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.111936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.111936 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -875,16 +880,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -893,210 +898,214 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4235 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits -system.cpu.icache.overall_hits::total 1585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses -system.cpu.icache.overall_misses::total 386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4216 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses +system.cpu.icache.overall_misses::total 384 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 21 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 21 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 38 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.cpu.l2cache.overall_misses::total 401 # number of overall misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 85 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 294 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 294 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.800000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.800000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938776 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,119 +1114,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 354 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 396 # Request fanout histogram +system.membus.snoop_fanout::samples 397 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index a8b793687..4403ba687 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -147,8 +149,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index fe4c1d834..a846c7a0c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18741000 # Number of ticks simulated -final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18821000 # Number of ticks simulated +final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 9099 # Simulator instruction rate (inst/s) host_op_rate 10656 # Simulator op (including micro ops) rate (op/s) @@ -13,34 +13,34 @@ sim_insts 4592 # Nu sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18432 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 288 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 441 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 983512086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 430286538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 92204258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506002881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 983512086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 983512086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 983512086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 430286538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 92204258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506002881 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442 # Number of read requests accepted +system.physmem.num_reads::total 443 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 442 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28288 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28288 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 101 # Per bank write bursts system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 44 # Per bank write bursts +system.physmem.perBankRdBursts::3 45 # Per bank write bursts system.physmem.perBankRdBursts::4 19 # Per bank write bursts system.physmem.perBankRdBursts::5 37 # Per bank write bursts system.physmem.perBankRdBursts::6 46 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18727500 # Total gap between requests +system.physmem.totGap 18779500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 442 # Read request sizes (log2) +system.physmem.readPktSize::6 443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,10 +94,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see @@ -191,77 +191,82 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 425.650794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 288.378165 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.476918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21 33.33% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 7.94% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3434000 # Total ticks spent queuing -system.physmem.totMemAccLat 11721500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2210000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7769.23 # Average queueing delay per DRAM burst +system.physmem.totQLat 3401243 # Total ticks spent queuing +system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26519.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1509.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1509.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.79 # Data bus utilization in percentage -system.physmem.busUtilRead 11.79 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.77 # Data bus utilization in percentage +system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 370 # Number of row buffer hits during reads +system.physmem.readRowHits 371 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42369.91 # Average gap between requests -system.physmem.pageHitRate 83.71 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42391.65 # Average gap between requests +system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10786680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 37500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14457615 # Total energy per rank (pJ) -system.physmem_0.averagePower 913.160587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states +system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) +system.physmem_0.averagePower 912.921838 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9859005 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 851250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12737220 # Total energy per rank (pJ) -system.physmem_1.averagePower 804.498342 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2184750 # Time in different power states +system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.289436 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13949750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2341 # Number of BP lookups -system.cpu.branchPred.condPredicted 1389 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups -system.cpu.branchPred.BTBHits 447 # Number of BTB hits +system.cpu.branchPred.lookups 2438 # Number of BP lookups +system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 449 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.341289 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -380,84 +385,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 37483 # number of cpu cycles simulated +system.cpu.numCycles 37643 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6059 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11274 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2341 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8204 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 363 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3834 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.845843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.199579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9385 60.16% 60.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2463 15.79% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 526 3.37% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3227 20.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.062455 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.300776 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5749 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5029 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9880 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1586 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6811 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1118 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2339 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4089 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 417 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5178 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 772 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9259 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40331 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9781 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41158 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3765 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1800 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1272 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3018 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7856 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15601 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.458176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.848338 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11391 73.01% 73.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1965 12.60% 85.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1598 10.24% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 601 3.85% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 46 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -465,147 +470,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 413 28.70% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 475 33.01% 61.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 551 38.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4480 62.67% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1582 22.13% 84.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1078 15.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7148 # Type of FU issued -system.cpu.iq.rate 0.190700 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1439 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.201315 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6562 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7234 # Type of FU issued +system.cpu.iq.rate 0.192174 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8559 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 773 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 334 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 385 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8410 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1800 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1272 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6751 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1398 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2419 # number of memory reference insts executed -system.cpu.iew.exec_branches 1275 # Number of branches executed -system.cpu.iew.exec_stores 1021 # Number of stores executed -system.cpu.iew.exec_rate 0.180108 # Inst execution rate -system.cpu.iew.wb_sent 6621 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6578 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2993 # num instructions producing a value -system.cpu.iew.wb_consumers 5408 # num instructions consuming a value -system.cpu.iew.wb_rate 0.175493 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553439 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2586 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 13 # number of nop insts executed +system.cpu.iew.exec_refs 2451 # number of memory reference insts executed +system.cpu.iew.exec_branches 1299 # Number of branches executed +system.cpu.iew.exec_stores 1030 # Number of stores executed +system.cpu.iew.exec_rate 0.181282 # Inst execution rate +system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6637 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2986 # num instructions producing a value +system.cpu.iew.wb_consumers 5424 # num instructions consuming a value +system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.357176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.003286 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12412 82.43% 82.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1386 9.21% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 592 3.93% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 296 1.97% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 173 1.15% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.52% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.30% 99.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.21% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -652,122 +657,122 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22821 # The number of ROB reads -system.cpu.rob.rob_writes 16478 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21882 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23088 # The number of ROB reads +system.cpu.rob.rob_writes 16743 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.162674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.162674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.122509 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.122509 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6723 # number of integer regfile reads -system.cpu.int_regfile_writes 3755 # number of integer regfile writes +system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads +system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6777 # number of integer regfile reads +system.cpu.int_regfile_writes 3787 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23977 # number of cc regfile reads -system.cpu.cc_regfile_writes 2903 # number of cc regfile writes -system.cpu.misc_regfile_reads 2611 # number of misc regfile reads +system.cpu.cc_regfile_reads 24229 # number of cc regfile reads +system.cpu.cc_regfile_writes 2921 # number of cc regfile writes +system.cpu.misc_regfile_reads 2586 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.551975 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1908 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.342657 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.551975 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.165141 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.165141 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4677 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1166 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1888 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1888 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1888 # number of overall hits -system.cpu.dcache.overall_hits::total 1888 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits +system.cpu.dcache.overall_hits::total 1910 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses -system.cpu.dcache.overall_misses::total 357 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10689500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10689500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7727500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7727500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses +system.cpu.dcache.overall_misses::total 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18417000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18417000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18417000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18417000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124625 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.124625 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159020 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159020 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159020 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159020 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64394.578313 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64394.578313 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40458.115183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40458.115183 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51588.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51588.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51588.235294 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 846 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -776,122 +781,122 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9436000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9436000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9436000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9436000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077327 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064143 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064143 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064143 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67854.368932 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67854.368932 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59682.926829 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59682.926829 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65527.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65527.777778 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 43 # number of replacements -system.cpu.icache.tags.tagsinuse 137.647063 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3470 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.722973 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 44 # number of replacements +system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.647063 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268842 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7960 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7960 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3470 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3470 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3470 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3470 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3470 # number of overall hits -system.cpu.icache.overall_hits::total 3470 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22661491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22661491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22661491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22661491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22661491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22661491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62600.803867 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62600.803867 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62600.803867 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62600.803867 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62600.803867 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8953 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits +system.cpu.icache.overall_hits::total 3540 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses +system.cpu.icache.overall_misses::total 361 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22435492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22435492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22435492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22435492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22435492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22435492 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092540 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092540 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092540 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092540 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092540 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092540 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62148.177285 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62148.177285 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62148.177285 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.260417 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 43 # number of writebacks -system.cpu.icache.writebacks::total 43 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19893491 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19893491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19893491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19893491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19893491 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19893491 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077505 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077505 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077505 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077505 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66981.451178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66981.451178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66981.451178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66981.451178 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 44 # number of writebacks +system.cpu.icache.writebacks::total 44 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19775992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19775992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -900,16 +905,16 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 19.860815 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.208333 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.229167 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.581774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.279041 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000646 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001212 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000645 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001209 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -918,84 +923,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7643 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7643 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 7 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 20 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits +system.cpu.l2cache.demand_hits::total 21 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits -system.cpu.l2cache.overall_hits::total 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 21 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 290 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 290 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 290 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 421 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 290 # number of overall misses +system.cpu.l2cache.demand_misses::total 422 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses -system.cpu.l2cache.overall_misses::total 421 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2313000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2313000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19544000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 19544000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6815000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6815000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9128000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9128000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28672000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 422 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2299000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2299000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19417500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 19417500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6760500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6760500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19417500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9059500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28477000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19417500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9059500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28477000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 297 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 297 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976431 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976431 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976431 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.954649 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976431 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.952596 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.954649 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77100 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77100 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67393.103448 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67393.103448 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67475.247525 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67475.247525 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68104.513064 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67393.103448 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69679.389313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68104.513064 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.952596 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76633.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76633.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66726.804124 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66726.804124 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66935.643564 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66935.643564 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67481.042654 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,123 +1023,123 @@ system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 289 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 289 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2133000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2133000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17760500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17760500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5946500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5946500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17760500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17760500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27465926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1908926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2119000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2119000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.973064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.941043 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.973064 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.061224 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 30677.849057 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71100 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71100 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61455.017301 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61455.017301 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61942.708333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61942.708333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62265.060241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61455.017301 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64123.015873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 30677.849057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58687.876068 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 452 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.582857 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 454 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 443 49.61% 49.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 409 45.80% 95.41% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41 4.59% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 893 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 286500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 444499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 410 # Transaction distribution +system.membus.trans_dist::ReadResp 412 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 882 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 442 # Request fanout histogram +system.membus.snoop_fanout::samples 443 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 442 # Request fanout histogram -system.membus.reqLayer0.occupancy 559944 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 443 # Request fanout histogram +system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2320000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 49256c4fe..60fb7fd34 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -401,6 +403,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 7af27520b..40d4f88c7 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -251,6 +253,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 21e554bfb..3fd071b25 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -29,6 +29,8 @@ multi_thread=false num_work_ids=16 readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -381,6 +381,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 |