diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/quick/se/00.hello/ref/arm/linux | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux')
3 files changed, 687 insertions, 687 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index e5ff065c1..3e86bd3ac 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29934500 # Number of ticks simulated -final_tick 29934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29941500 # Number of ticks simulated +final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115469 # Simulator instruction rate (inst/s) -host_op_rate 135130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 750106498 # Simulator tick rate (ticks/s) -host_mem_usage 310152 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 58660 # Simulator instruction rate (inst/s) +host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 381226078 # Simulator tick rate (ticks/s) +host_mem_usage 304332 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 652090397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 248008151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 900098548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 652090397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 652090397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 652090397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 248008151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 900098548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29844000 # Total gap between requests +system.physmem.totGap 29851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2214000 # Total ticks spent queuing -system.physmem.totMemAccLat 10107750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2218000 # Total ticks spent queuing +system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5258.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24008.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 900.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 900.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70888.36 # Average gap between requests +system.physmem.avgGap 70904.99 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -250,14 +250,14 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1918 # Number of BP lookups -system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 336 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1604 # Number of BTB lookups -system.cpu.branchPred.BTBHits 341 # Number of BTB hits +system.cpu.branchPred.lookups 1912 # Number of BP lookups +system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups +system.cpu.branchPred.BTBHits 347 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 21.259352 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59869 # number of cpu cycles simulated +system.cpu.numCycles 59883 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.000869 # CPI: cycles per instruction -system.cpu.ipc 0.076918 # IPC: instructions per cycle -system.cpu.tickCycles 10574 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49295 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.003909 # CPI: cycles per instruction +system.cpu.ipc 0.076900 # IPC: instructions per cycle +system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.493580 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.493580 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits +system.cpu.dcache.overall_hits::total 1893 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11975500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11975500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11975500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11975500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65799.450549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65799.450549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9551000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.765243 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.765243 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078987 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078987 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4784 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits -system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23594000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23594000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23594000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23594000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23594000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23594000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2231 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.144330 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.144330 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73273.291925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73273.291925 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23272000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23272000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23272000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23272000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23272000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23272000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.411120 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.281002 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.130118 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id @@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 # system.cpu.l2cache.overall_misses::total 429 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22610500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22610500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5960500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5960500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22610500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9094000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31704500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22610500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9094000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31704500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116 system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19560500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19560500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4700500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4700500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19560500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26964500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19560500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26964500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -731,16 +731,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index e4986f157..800acea54 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,14 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 14:33:28 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:30:05 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second - 0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0 - 0: system.cpu.isa: ISA system set to: 0 0x38f90a0 info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 17307500 because target called exit() +Exiting @ tick 17163000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 80e232875..be50d79db 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17226500 # Number of ticks simulated -final_tick 17226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17163000 # Number of ticks simulated +final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55427 # Simulator instruction rate (inst/s) -host_op_rate 64904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 207866253 # Simulator tick rate (ticks/s) -host_mem_usage 311436 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 25428 # Simulator instruction rate (inst/s) +host_op_rate 29777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95019968 # Simulator tick rate (ticks/s) +host_mem_usage 305352 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1021681711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449539953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1471221664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1021681711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1021681711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1021681711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449539953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1471221664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17159000 # Total gap between requests +system.physmem.totGap 17090000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 395.354839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 263.720067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.958245 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 30.65% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.68% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 12.90% 70.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 75.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.23% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.23% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.23% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3039250 # Total ticks spent queuing -system.physmem.totMemAccLat 10464250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3055250 # Total ticks spent queuing +system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7674.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26424.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1471.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1471.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43330.81 # Average gap between requests -system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43156.57 # Average gap between requests +system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10797795 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14404965 # Total energy per rank (pJ) -system.physmem_0.averagePower 909.404356 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states +system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.198611 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16109250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10359180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 412500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12771300 # Total energy per rank (pJ) -system.physmem_1.averagePower 806.650876 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 820250 # Time in different power states +system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) +system.physmem_1.averagePower 807.028896 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14680750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2576 # Number of BP lookups -system.cpu.branchPred.condPredicted 1602 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2087 # Number of BTB lookups -system.cpu.branchPred.BTBHits 781 # Number of BTB hits +system.cpu.branchPred.lookups 2533 # Number of BP lookups +system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups +system.cpu.branchPred.BTBHits 812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.422137 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,237 +496,237 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34454 # number of cpu cycles simulated +system.cpu.numCycles 34327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12205 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2016 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.088585 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.463952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10589 80.10% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.07% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 212 1.60% 83.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 221 1.67% 85.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 236 1.79% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 324 2.45% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 1.22% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1063 8.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.074766 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.354240 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2102 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2063 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11852 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6584 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2356 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2013 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1236 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11200 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1964 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1064 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11331 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5837 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 42 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10125 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4793 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13219 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.620471 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10002 75.66% 75.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1166 8.82% 84.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 755 5.71% 90.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 451 3.41% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.70% 96.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.10% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 63 0.48% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 16 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.26% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 49.12% 54.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 45.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4937 60.19% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1959 23.88% 84.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1297 15.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8202 # Type of FU issued -system.cpu.iq.rate 0.238057 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020849 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29750 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14855 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7430 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 7972 # Type of FU issued +system.cpu.iq.rate 0.232237 # Inst issue rate +system.cpu.iq.fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8330 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1260 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 660 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10180 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 234 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7868 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1843 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3072 # number of memory reference insts executed -system.cpu.iew.exec_branches 1434 # Number of branches executed -system.cpu.iew.exec_stores 1229 # Number of stores executed -system.cpu.iew.exec_rate 0.228362 # Inst execution rate -system.cpu.iew.wb_sent 7574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7462 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3524 # num instructions producing a value -system.cpu.iew.wb_consumers 6897 # num instructions consuming a value +system.cpu.iew.exec_refs 2930 # number of memory reference insts executed +system.cpu.iew.exec_branches 1433 # Number of branches executed +system.cpu.iew.exec_stores 1194 # Number of stores executed +system.cpu.iew.exec_rate 0.224226 # Inst execution rate +system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7341 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3456 # num instructions producing a value +system.cpu.iew.wb_consumers 6757 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.216579 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510947 # average fanout of values written-back +system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4801 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.434340 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.281233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10327 83.40% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 891 7.20% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 421 3.40% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 214 1.73% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 114 0.92% 96.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.71% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22289 # The number of ROB reads -system.cpu.rob.rob_writes 21210 # The number of ROB writes -system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 21783 # The number of ROB reads +system.cpu.rob.rob_writes 20313 # The number of ROB writes +system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.503049 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.503049 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133279 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133279 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7752 # number of integer regfile reads -system.cpu.int_regfile_writes 4259 # number of integer regfile writes +system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7631 # number of integer regfile reads +system.cpu.int_regfile_writes 4176 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28119 # number of cc regfile reads -system.cpu.cc_regfile_writes 3280 # number of cc regfile writes -system.cpu.misc_regfile_reads 3175 # number of misc regfile reads +system.cpu.cc_regfile_reads 27375 # number of cc regfile reads +system.cpu.cc_regfile_writes 3204 # number of cc regfile writes +system.cpu.misc_regfile_reads 3054 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.080084 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2156 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.767123 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.080084 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5466 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5466 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1537 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1537 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5255 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2134 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2134 # number of overall hits -system.cpu.dcache.overall_hits::total 2134 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2032 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2032 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2032 # number of overall hits +system.cpu.dcache.overall_hits::total 2032 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 181 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10668000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10668000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22567500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22567500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33235500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33235500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1723 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.111936 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.111936 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190440 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190440 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190440 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190440 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66206.175299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66206.175299 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,135 +895,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10091500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060940 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060940 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055766 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.175552 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1623 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.539249 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.175552 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072840 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4325 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4325 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1623 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1623 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1623 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1623 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1623 # number of overall hits -system.cpu.icache.overall_hits::total 1623 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 393 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 393 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 393 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 393 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 393 # number of overall misses -system.cpu.icache.overall_misses::total 393 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27030000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27030000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27030000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27030000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27030000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27030000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2016 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2016 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2016 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194940 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194940 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194940 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194940 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194940 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194940 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68778.625954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68778.625954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68778.625954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68778.625954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4229 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits +system.cpu.icache.overall_hits::total 1582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses +system.cpu.icache.overall_misses::total 386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145337 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145337 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145337 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73624.573379 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73624.573379 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73624.573379 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73624.573379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73624.573379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73624.573379 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.076752 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.018845 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.057907 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses @@ -1049,18 +1049,18 @@ system.cpu.l2cache.demand_misses::total 401 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses system.cpu.l2cache.overall_misses::total 401 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20942500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20942500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6371000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6371000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20942500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20942500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30656000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) @@ -1085,18 +1085,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.911364 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76154.545455 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75845.238095 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75845.238095 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76154.545455 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77091.269841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76448.877805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76154.545455 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77091.269841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76448.877805 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1123,18 +1123,18 @@ system.cpu.l2cache.demand_mshr_misses::total 396 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18192500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18192500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5250500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5250500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8173000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26365500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18192500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8173000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26365500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses @@ -1147,30 +1147,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 879 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram @@ -1187,7 +1187,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 220500 # La system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1210,7 +1210,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 396 # Request fanout histogram system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2095750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |