diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/00.hello/ref/arm/linux | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux')
6 files changed, 1469 insertions, 1201 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 1f9a90b5a..58622e09f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27981000 # Number of ticks simulated final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65720 # Simulator instruction rate (inst/s) -host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399296424 # Simulator tick rate (ticks/s) -host_mem_usage 250660 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 95550 # Simulator instruction rate (inst/s) +host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 580422337 # Simulator tick rate (ticks/s) +host_mem_usage 309164 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -217,29 +217,34 @@ system.physmem.readRowHitRate 83.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 66260.10 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22840500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) -system.physmem.averagePower::0 856.107753 # Core power per rank (mW) -system.physmem.averagePower::1 786.272135 # Core power per rank (mW) +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) +system.physmem_0.averagePower 856.107753 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) +system.physmem_1.averagePower 786.272135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1926 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect @@ -250,6 +255,14 @@ system.cpu.branchPred.BTBHitPct 20.426065 # BT system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -271,6 +284,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -292,6 +313,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,6 +342,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 62f6dcd2b..bac015830 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26356 # Simulator instruction rate (inst/s) -host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93111675 # Simulator tick rate (ticks/s) -host_mem_usage 251576 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 54860 # Simulator instruction rate (inst/s) +host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193800024 # Simulator tick rate (ticks/s) +host_mem_usage 308908 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.38 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 40695.21 # Average gap between requests system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) -system.physmem.averagePower::0 920.354334 # Core power per rank (mW) -system.physmem.averagePower::1 810.522027 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) +system.physmem_0.averagePower 920.354334 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) +system.physmem_1.averagePower 810.522027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2638 # Number of BP lookups system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect @@ -277,6 +258,15 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -298,6 +288,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -319,6 +317,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -340,6 +346,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -365,6 +379,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5390 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -386,6 +408,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -407,6 +437,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -428,6 +466,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -744,42 +790,136 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. @@ -1010,135 +1150,64 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6fc5d6de3..9157ec7b3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11859500 # Number of ticks simulated -final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16487000 # Number of ticks simulated +final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34923 # Simulator instruction rate (inst/s) -host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90188816 # Simulator tick rate (ticks/s) -host_mem_usage 248256 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 33036 # Simulator instruction rate (inst/s) +host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118603969 # Simulator tick rate (ticks/s) +host_mem_usage 248576 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory -system.physmem.bytes_read::total 46848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 732 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 733 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory +system.physmem.bytes_read::total 26048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 143 # Per bank write bursts -system.physmem.perBankRdBursts::1 90 # Per bank write bursts -system.physmem.perBankRdBursts::2 40 # Per bank write bursts -system.physmem.perBankRdBursts::3 73 # Per bank write bursts -system.physmem.perBankRdBursts::4 58 # Per bank write bursts -system.physmem.perBankRdBursts::5 88 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 18 # Per bank write bursts -system.physmem.perBankRdBursts::8 12 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::0 88 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 19 # Per bank write bursts +system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts +system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 26 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 19 # Per bank write bursts +system.physmem.perBankRdBursts::13 7 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11846500 # Total gap between requests +system.physmem.totGap 16473500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 733 # Read request sizes (log2) +system.physmem.readPktSize::6 408 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation -system.physmem.totQLat 17284989 # Total ticks spent queuing -system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3192729 # Total ticks spent queuing +system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 30.90 # Data bus utilization in percentage -system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.37 # Data bus utilization in percentage +system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 662 # Number of row buffer hits during reads +system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16161.66 # Average gap between requests -system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 6500 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7800750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) -system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) -system.physmem.averagePower::1 892.270681 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 704 # Transaction distribution -system.membus.trans_dist::ReadResp 702 # Transaction distribution -system.membus.trans_dist::ReadExReq 29 # Transaction distribution -system.membus.trans_dist::ReadExResp 29 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 733 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 733 # Request fanout histogram -system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 55.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2560 # Number of BP lookups -system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups -system.cpu.branchPred.BTBHits 497 # Number of BTB hits +system.physmem.avgGap 40376.23 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) +system.physmem_0.averagePower 918.403600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) +system.physmem_1.averagePower 817.101847 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 2361 # Number of BP lookups +system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 473 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 23720 # number of cpu cycles simulated +system.cpu.numCycles 32975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4080 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -452,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7242 # Type of FU issued -system.cpu.iq.rate 0.305312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 7157 # Type of FU issued +system.cpu.iq.rate 0.217043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2449 # number of memory reference insts executed -system.cpu.iew.exec_branches 1283 # Number of branches executed -system.cpu.iew.exec_stores 1021 # Number of stores executed -system.cpu.iew.exec_rate 0.287858 # Inst execution rate -system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3045 # num instructions producing a value -system.cpu.iew.wb_consumers 5519 # num instructions consuming a value +system.cpu.iew.exec_refs 2417 # number of memory reference insts executed +system.cpu.iew.exec_branches 1277 # Number of branches executed +system.cpu.iew.exec_stores 1017 # Number of stores executed +system.cpu.iew.exec_rate 0.205034 # Inst execution rate +system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6587 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2990 # num instructions producing a value +system.cpu.iew.wb_consumers 5391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back +system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -640,449 +654,469 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16750 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22003 # The number of ROB reads +system.cpu.rob.rob_writes 16441 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads -system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6787 # number of integer regfile reads -system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6737 # number of integer regfile reads +system.cpu.int_regfile_writes 3765 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24301 # number of cc regfile reads -system.cpu.cc_regfile_writes 2919 # number of cc regfile writes -system.cpu.misc_regfile_reads 2642 # number of misc regfile reads +system.cpu.cc_regfile_reads 24010 # number of cc regfile reads +system.cpu.cc_regfile_writes 2910 # number of cc regfile writes +system.cpu.misc_regfile_reads 2599 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1026 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 47 # number of replacements -system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits +system.cpu.dcache.overall_hits::total 1876 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses +system.cpu.dcache.overall_misses::total 369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 226 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8536 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits -system.cpu.icache.overall_hits::total 3784 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 304 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits -system.cpu.dcache.overall_hits::total 1873 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses -system.cpu.dcache.overall_misses::total 392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 67 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.membus.trans_dist::ReadExReq 30 # Transaction distribution +system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 408 # Request fanout histogram +system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 23.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 398374723..72322cbec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582910 # Simulator instruction rate (inst/s) -host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 341032781 # Simulator tick rate (ticks/s) -host_mem_usage 293692 # Number of bytes of host memory used +host_inst_rate 396323 # Simulator instruction rate (inst/s) +host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232084410 # Simulator tick rate (ticks/s) +host_mem_usage 298640 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index d2d36b722..b8c713e42 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 685428 # Simulator instruction rate (inst/s) -host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 400788339 # Simulator tick rate (ticks/s) -host_mem_usage 292412 # Number of bytes of host memory used +host_inst_rate 370272 # Simulator instruction rate (inst/s) +host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216878622 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -209,5 +213,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 83a7fcb5f..872a056d2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 367819 # Simulator instruction rate (inst/s) -host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075494452 # Simulator tick rate (ticks/s) -host_mem_usage 302164 # Number of bytes of host memory used +host_inst_rate 376930 # Simulator instruction rate (inst/s) +host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2127142386 # Simulator tick rate (ticks/s) +host_mem_usage 307352 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 307 # Transaction distribution -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,118 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits +system.cpu.dcache.overall_hits::total 1764 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. @@ -416,118 +537,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -560,5 +569,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram +system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |