diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/se/00.hello/ref/arm | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
24 files changed, 835 insertions, 377 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index 0858c144d..a47bafcf6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -59,6 +64,7 @@ decodeCycleInput=true decodeInputBufferSize=3 decodeInputWidth=2 decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -103,12 +109,17 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false system=system +threadPolicy=RoundRobin tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -144,12 +155,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +184,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -192,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -208,9 +234,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -604,12 +635,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -628,8 +664,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -687,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -703,9 +749,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -716,12 +767,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -740,8 +796,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 @@ -749,10 +810,15 @@ size=2097152 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -783,7 +849,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -815,10 +881,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -862,6 +933,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -873,7 +945,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr index 341b479f7..bbcd9d751 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr @@ -1,2 +1,3 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index b3cb615d2..21abd8071 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:59 -gem5 executing on zizzer, pid 20780 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23083 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 29949500 because target called exit() +Exiting @ tick 30083500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index acde8b0d6..ebafeb85e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29977500 # Number of ticks simulated -final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30083500 # Number of ticks simulated +final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147440 # Simulator instruction rate (inst/s) -host_op_rate 172555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 959274014 # Simulator tick rate (ticks/s) -host_mem_usage 309288 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 80042 # Simulator instruction rate (inst/s) +host_op_rate 93682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 522670316 # Simulator tick rate (ticks/s) +host_mem_usage 264608 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29886000 # Total gap between requests +system.physmem.totGap 29992500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -189,84 +189,84 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2113500 # Total ticks spent queuing -system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2221000 # Total ticks spent queuing +system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.02 # Data bus utilization in percentage -system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.00 # Data bus utilization in percentage +system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 350 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70988.12 # Average gap between requests +system.physmem.avgGap 71241.09 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20068140 # Total energy per rank (pJ) -system.physmem_0.averagePower 849.669860 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states +system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ) +system.physmem_0.averagePower 849.295873 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ) -system.physmem_1.averagePower 784.269066 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states +system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ) +system.physmem_1.averagePower 783.273247 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1949 # Number of BP lookups -system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1968 # Number of BP lookups +system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 316 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1660 # Number of BTB lookups +system.cpu.branchPred.BTBHits 322 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.397590 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 125 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29977500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59955 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 60167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.019544 # CPI: cycles per instruction -system.cpu.ipc 0.076808 # IPC: instructions per cycle +system.cpu.cpi 13.065581 # CPI: cycles per instruction +system.cpu.ipc 0.076537 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -432,95 +432,95 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits -system.cpu.dcache.overall_hits::total 1894 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses +system.cpu.dcache.overall_misses::total 176 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2072 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2072 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2072 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2072 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses @@ -529,83 +529,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4821 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits -system.cpu.icache.overall_hits::total 1926 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses -system.cpu.icache.overall_misses::total 323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4892 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1963 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1963 # number of overall hits +system.cpu.icache.overall_hits::total 1963 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses +system.cpu.icache.overall_misses::total 322 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2285 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2285 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2285 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140919 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.140919 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,61 +614,61 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 4 # number of writebacks system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::total 39 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses @@ -681,56 +681,56 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,80 +755,81 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -838,6 +839,7 @@ system.membus.pkt_count::total 842 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 421 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram @@ -848,9 +850,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index db680b227..78e5f6bf3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -72,6 +77,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 +default_p_state=UNDEFINED dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -110,6 +116,10 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -168,6 +178,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -186,6 +197,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -216,9 +231,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker [system.cpu.checker.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.dtb] @@ -232,9 +252,14 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[5] @@ -288,9 +313,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker [system.cpu.checker.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.itb] @@ -304,9 +334,14 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[4] @@ -321,12 +356,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -345,8 +385,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -369,9 +414,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -385,9 +435,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -705,12 +760,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -729,8 +789,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -788,9 +853,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -804,9 +874,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -817,12 +892,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -841,8 +921,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 @@ -850,10 +935,15 @@ size=2097152 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -884,7 +974,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -916,10 +1006,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -963,6 +1058,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -974,7 +1070,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr index 341b479f7..57447a9b7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -1,2 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 97296d3da..8c38643eb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:35:59 -gem5 started Mar 13 2016 22:47:14 -gem5 executing on phenom, pid 19877 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:41:21 +gem5 executing on e108600-lin, pid 23122 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index e232e499c..f9ef4c918 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78702 # Simulator instruction rate (inst/s) -host_op_rate 92158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 295258113 # Simulator tick rate (ticks/s) -host_mem_usage 310332 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 43349 # Simulator instruction rate (inst/s) +host_op_rate 50759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162616088 # Simulator tick rate (ticks/s) +host_mem_usage 265888 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1198,6 +1198,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram @@ -1225,6 +1226,7 @@ system.membus.pkt_count::total 794 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 397 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 4403ba687..fc0ffed98 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -72,6 +77,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -110,6 +116,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -190,8 +205,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -532,8 +567,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -607,9 +652,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu.l2cache.prefetcher response_latency=12 @@ -643,6 +698,7 @@ mem_side=system.membus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -653,6 +709,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -669,8 +729,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -678,10 +743,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -712,7 +782,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -744,10 +814,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -791,6 +866,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -802,7 +878,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=0:134217727 ranks_per_channel=2 read_buffer_size=32 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr index 341b479f7..bbcd9d751 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index e4ae04024..10d18de27 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:35:59 -gem5 started Mar 13 2016 22:47:14 -gem5 executing on phenom, pid 19874 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:07:36 +gem5 executing on e108600-lin, pid 24410 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index e81d385ba..1e33086fd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84019 # Simulator instruction rate (inst/s) -host_op_rate 98384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 344256847 # Simulator tick rate (ticks/s) -host_mem_usage 306884 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 60061 # Simulator instruction rate (inst/s) +host_op_rate 70319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 246027411 # Simulator tick rate (ticks/s) +host_mem_usage 262688 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1107,6 +1107,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 454 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram @@ -1134,6 +1135,7 @@ system.membus.pkt_count::total 885 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 443 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 60fb7fd34..be532b0c0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=system.cpu.checker clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -73,6 +79,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -93,6 +103,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=-1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -111,6 +122,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -141,9 +156,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker [system.cpu.checker.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.dtb] @@ -157,9 +177,14 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.isa] @@ -212,9 +237,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker [system.cpu.checker.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.itb] @@ -228,9 +258,14 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.checker.tracer] @@ -256,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -272,9 +312,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[4] @@ -332,9 +377,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -348,9 +398,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[3] @@ -368,7 +423,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -400,10 +455,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -418,11 +478,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index 1a4f96712..2b0e974b5 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index dca8243ae..a4f08df89 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:47:11 -gem5 executing on zizzer, pid 20787 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:47 +gem5 executing on e108600-lin, pid 23301 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index c4cb1f552..55d542711 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 569364 # Simulator instruction rate (inst/s) -host_op_rate 666035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 333433301 # Simulator tick rate (ticks/s) -host_mem_usage 299296 # Number of bytes of host memory used +host_inst_rate 427598 # Simulator instruction rate (inst/s) +host_op_rate 499586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249859240 # Simulator tick rate (ticks/s) +host_mem_usage 254616 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated @@ -359,6 +359,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 40d4f88c7..8f8064fa0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -73,6 +79,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[4] @@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -198,9 +223,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.membus.slave[3] @@ -218,7 +248,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -250,10 +280,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -268,11 +303,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr index 1a4f96712..aadc3d011 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 98eb95060..813c1fdca 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:25 -gem5 executing on zizzer, pid 20745 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:23 +gem5 executing on e108600-lin, pid 23087 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index a84dba320..43260b12f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 625339 # Simulator instruction rate (inst/s) -host_op_rate 731490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 366164896 # Simulator tick rate (ticks/s) -host_mem_usage 298280 # Number of bytes of host memory used +host_inst_rate 433184 # Simulator instruction rate (inst/s) +host_op_rate 506134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 253162440 # Simulator tick rate (ticks/s) +host_mem_usage 254364 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated @@ -235,6 +235,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 3fd071b25..b1081da03 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -72,6 +78,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -114,8 +129,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=262144 @@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -191,8 +226,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=131072 @@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -266,9 +311,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -303,8 +358,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=2097152 @@ -312,10 +372,15 @@ size=2097152 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -346,7 +411,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false @@ -378,10 +443,15 @@ transition_latency=100000000 [system.membus] type=CoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -396,11 +466,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:134217727 port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr index 1a4f96712..aadc3d011 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index daa769407..4f7f76cdc 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:20 -gem5 executing on zizzer, pid 20726 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:23 +gem5 executing on e108600-lin, pid 23085 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 92414aab2..40170ff2c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377704 # Simulator instruction rate (inst/s) -host_op_rate 440559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2337429945 # Simulator tick rate (ticks/s) -host_mem_usage 308268 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 246555 # Simulator instruction rate (inst/s) +host_op_rate 287459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1524533550 # Simulator tick rate (ticks/s) +host_mem_usage 264352 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -573,6 +573,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram @@ -600,6 +601,7 @@ system.membus.pkt_count::total 700 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 350 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram |