diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-20 16:48:19 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-20 16:48:19 -0500 |
commit | d2a0f60b69313ad869f81fb006c8e998e40cb3c1 (patch) | |
tree | 39b323ea65cc3c21cf3b00a05df44bcec214c580 /tests/quick/se/00.hello/ref/arm | |
parent | 922a9d8ed2488a3483dbbfff47a4f341fb707b7b (diff) | |
download | gem5-d2a0f60b69313ad869f81fb006c8e998e40cb3c1.tar.xz |
stats: updates due to previous mmap and exit_group patches.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
6 files changed, 46 insertions, 46 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 54adfc503..d08d4e917 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -371,9 +371,9 @@ system.cpu.tickCycles 10521 # Nu system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy @@ -382,14 +382,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 318 system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4801 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4799 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits +system.cpu.icache.overall_hits::total 1918 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses @@ -402,18 +402,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 21503250 system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency @@ -440,12 +440,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 092386ab8..62f6dcd2b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -457,7 +457,7 @@ system.cpu.fetch.Insts 12484 # Nu system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR @@ -728,7 +728,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21719 # The number of ROB writes +system.cpu.rob.rob_writes 21720 # The number of ROB writes system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated @@ -737,7 +737,7 @@ system.cpu.cpi 7.067523 # CP system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7944 # number of integer regfile reads +system.cpu.int_regfile_reads 7945 # number of integer regfile reads system.cpu.int_regfile_writes 4420 # number of integer regfile writes system.cpu.fp_regfile_reads 31 # number of floating regfile reads system.cpu.cc_regfile_reads 28734 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ce3916e93..6fc5d6de3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -375,7 +375,7 @@ system.cpu.fetch.Insts 12370 # Nu system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR @@ -643,7 +643,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16749 # The number of ROB writes +system.cpu.rob.rob_writes 16750 # The number of ROB writes system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated @@ -652,7 +652,7 @@ system.cpu.cpi 5.166630 # CP system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6786 # number of integer regfile reads +system.cpu.int_regfile_reads 6787 # number of integer regfile reads system.cpu.int_regfile_writes 3839 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.cc_regfile_reads 24301 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 9b7b2bcb6..398374723 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -256,10 +256,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5390 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 73cde8525..d2d36b722 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -169,10 +169,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5390 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 8f2c9257f..83a7fcb5f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 51630 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction |