diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/quick/se/00.hello/ref/arm | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
3 files changed, 1168 insertions, 1168 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 4822d2cee..680b47747 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32719500 # Number of ticks simulated -final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32617500 # Number of ticks simulated +final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128948 # Simulator instruction rate (inst/s) -host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 915725978 # Simulator tick rate (ticks/s) -host_mem_usage 269308 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 159604 # Simulator instruction rate (inst/s) +host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1129633158 # Simulator tick rate (ticks/s) +host_mem_usage 268376 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 421 # Number of read requests accepted +system.physmem.num_reads::total 420 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 420 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -46,7 +46,7 @@ system.physmem.perBankRdBursts::0 91 # Pe system.physmem.perBankRdBursts::1 52 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts +system.physmem.perBankRdBursts::4 21 # Per bank write bursts system.physmem.perBankRdBursts::5 41 # Per bank write bursts system.physmem.perBankRdBursts::6 36 # Per bank write bursts system.physmem.perBankRdBursts::7 12 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32621500 # Total gap between requests +system.physmem.totGap 32519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 421 # Read request sizes (log2) +system.physmem.readPktSize::6 420 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5175000 # Total ticks spent queuing -system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst +system.physmem.totQLat 5148000 # Total ticks spent queuing +system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.43 # Data bus utilization in percentage -system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.44 # Data bus utilization in percentage +system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 347 # Number of row buffer hits during reads +system.physmem.readRowHits 346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77485.75 # Average gap between requests -system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined +system.physmem.avgGap 77427.38 # Average gap between requests +system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ) -system.physmem_0.averagePower 615.992054 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) +system.physmem_0.averagePower 616.275926 # Core power per rank (mW) +system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ) -system.physmem_1.averagePower 556.500000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) +system.physmem_1.averagePower 557.213152 # Core power per rank (mW) +system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1968 # Number of BP lookups -system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups -system.cpu.branchPred.BTBHits 322 # Number of BTB hits +system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1965 # Number of BP lookups +system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 324 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65439 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 65235 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.210423 # CPI: cycles per instruction -system.cpu.ipc 0.070371 # IPC: instructions per cycle +system.cpu.cpi 14.166124 # CPI: cycles per instruction +system.cpu.ipc 0.070591 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -446,25 +446,25 @@ system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -567,59 +567,59 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4896 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits -system.cpu.icache.overall_hits::total 1965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses -system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles +system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4895 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits +system.cpu.icache.overall_hits::total 1966 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses +system.cpu.icache.overall_misses::total 321 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,49 +628,49 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 4 # number of writebacks system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -685,66 +685,66 @@ system.cpu.l2cache.overall_hits::cpu.data 22 # n system.cpu.l2cache.overall_hits::total 39 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses +system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 429 # number of overall misses +system.cpu.l2cache.overall_misses::total 428 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,120 +759,120 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 8 system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 378 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 421 # Request fanout histogram +system.membus.snoop_fanout::samples 420 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 420 # Request fanout histogram +system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 5d8a28b22..bd3252a40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18422500 # Number of ticks simulated -final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18517500 # Number of ticks simulated +final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76941 # Simulator instruction rate (inst/s) -host_op_rate 90095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 308579581 # Simulator tick rate (ticks/s) -host_mem_usage 270584 # Number of bytes of host memory used +host_inst_rate 74881 # Simulator instruction rate (inst/s) +host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 301872470 # Simulator tick rate (ticks/s) +host_mem_usage 270416 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.num_reads::total 396 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::5 32 # Pe system.physmem.perBankRdBursts::6 35 # Per bank write bursts system.physmem.perBankRdBursts::7 10 # Per bank write bursts system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 9 # Per bank write bursts +system.physmem.perBankRdBursts::9 8 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 42 # Per bank write bursts system.physmem.perBankRdBursts::12 10 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18337000 # Total gap between requests +system.physmem.totGap 18432000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,95 +188,95 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5196750 # Total ticks spent queuing -system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 5212000 # Total ticks spent queuing +system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.77 # Data bus utilization in percentage -system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.69 # Data bus utilization in percentage +system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 329 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46188.92 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46545.45 # Average gap between requests +system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) -system.physmem_0.averagePower 660.613923 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) +system.physmem_0.averagePower 659.559336 # Core power per rank (mW) +system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) -system.physmem_1.averagePower 569.303026 # Core power per rank (mW) -system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) +system.physmem_1.averagePower 567.626569 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2844 # Number of BP lookups -system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups -system.cpu.branchPred.BTBHits 867 # Number of BTB hits +system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2820 # Number of BP lookups +system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups +system.cpu.branchPred.BTBHits 844 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,11 +397,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -461,7 +461,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,245 +521,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36846 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 37036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2146 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2138 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 44.00% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62 41.33% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 91.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 8.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 14.25% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8096 # Type of FU issued -system.cpu.iq.rate 0.219725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8207 # Type of FU issued +system.cpu.iq.rate 0.221595 # Inst issue rate +system.cpu.iq.fu_busy_cnt 166 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2921 # number of memory reference insts executed -system.cpu.iew.exec_branches 1491 # Number of branches executed -system.cpu.iew.exec_stores 1153 # Number of stores executed -system.cpu.iew.exec_rate 0.211855 # Inst execution rate -system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7436 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3503 # num instructions producing a value -system.cpu.iew.wb_consumers 6835 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3007 # number of memory reference insts executed +system.cpu.iew.exec_branches 1490 # Number of branches executed +system.cpu.iew.exec_stores 1167 # Number of stores executed +system.cpu.iew.exec_rate 0.212901 # Inst execution rate +system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7470 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3518 # num instructions producing a value +system.cpu.iew.wb_consumers 6872 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -810,120 +810,120 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22637 # The number of ROB reads -system.cpu.rob.rob_writes 21308 # The number of ROB writes -system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22825 # The number of ROB reads +system.cpu.rob.rob_writes 21580 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7656 # number of integer regfile reads -system.cpu.int_regfile_writes 4268 # number of integer regfile writes +system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads +system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7779 # number of integer regfile reads +system.cpu.int_regfile_writes 4297 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27780 # number of cc regfile reads -system.cpu.cc_regfile_writes 3273 # number of cc regfile writes -system.cpu.misc_regfile_reads 2974 # number of misc regfile reads +system.cpu.cc_regfile_reads 28140 # number of cc regfile reads +system.cpu.cc_regfile_writes 3276 # number of cc regfile writes +system.cpu.misc_regfile_reads 3029 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits -system.cpu.dcache.overall_hits::total 2072 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits +system.cpu.dcache.overall_hits::total 2137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses -system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -932,140 +932,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4218 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses -system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4257 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits +system.cpu.icache.overall_hits::total 1587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses +system.cpu.icache.overall_misses::total 395 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913832 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938776 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.099773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300038 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 397 90.02% 90.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 9.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 355 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::samples 396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 396 # Request fanout histogram +system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 307f14079..bc5d2d1fc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20302000 # Number of ticks simulated final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10367 # Simulator instruction rate (inst/s) -host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45828431 # Simulator tick rate (ticks/s) -host_mem_usage 248616 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host +host_inst_rate 93691 # Simulator instruction rate (inst/s) +host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 414022055 # Simulator tick rate (ticks/s) +host_mem_usage 265936 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -205,12 +205,12 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6124000 # Total ticks spent queuing -system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6135000 # Total ticks spent queuing +system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s @@ -232,28 +232,28 @@ system.physmem_0.preEnergy 170775 # En system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) @@ -267,12 +267,12 @@ system.physmem_1.memoryStateTime::ACT 2792000 # Ti system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups +system.cpu.branchPred.BTBHits 446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -405,80 +405,80 @@ system.cpu.pwrStateResidencyTicks::ON 20302000 # Cu system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5174 # Number of cycles decode is running +system.cpu.decode.RunCycles 5171 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.RunCycles 4182 # Number of cycles rename is running system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7222 # Type of FU issued -system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.FU_type_0::total 7227 # Type of FU issued +system.cpu.iq.rate 0.177983 # Inst issue rate system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2442 # number of memory reference insts executed -system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_refs 2443 # number of memory reference insts executed +system.cpu.iew.exec_branches 1299 # Number of branches executed system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.167836 # Inst execution rate -system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6631 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5426 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.iew.exec_rate 0.168033 # Inst execution rate +system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6639 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2983 # num instructions producing a value +system.cpu.iew.wb_consumers 5430 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle @@ -635,7 +635,7 @@ system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23226 # The number of ROB reads -system.cpu.rob.rob_writes 16730 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23224 # The number of ROB reads +system.cpu.rob.rob_writes 16731 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6765 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.int_regfile_reads 6850 # number of integer regfile reads +system.cpu.int_regfile_writes 3795 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24202 # number of cc regfile reads -system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558 # number of misc regfile reads +system.cpu.cc_regfile_reads 24229 # number of cc regfile reads +system.cpu.cc_regfile_writes 2927 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id @@ -720,38 +720,38 @@ system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits -system.cpu.dcache.overall_hits::total 1906 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits +system.cpu.dcache.overall_hits::total 1903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses +system.cpu.dcache.overall_misses::total 361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -764,26 +764,26 @@ system.cpu.dcache.demand_accesses::cpu.data 2264 # system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,16 +792,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -826,67 +826,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8095 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits -system.cpu.icache.overall_hits::total 3536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits +system.cpu.icache.overall_hits::total 3532 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked @@ -895,36 +895,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -934,16 +934,16 @@ system.cpu.l2cache.prefetcher.pfRemovedFull 0 # system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -981,16 +981,16 @@ system.cpu.l2cache.overall_misses::cpu.data 133 # system.cpu.l2cache.overall_misses::total 424 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1019,16 +1019,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1064,17 +1064,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1094,17 +1094,17 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1173,7 +1173,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |