stats: updates due to recent changes.

4 files changed, 93 insertions, 106 deletions

diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index 3d022001c..6229ef3c3 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -125,10 +125,9 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -137,7 +136,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -148,7 +147,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -588,7 +586,7 @@ eventq_index=0
 opClass=InstPrefetch
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -597,7 +595,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -608,7 +606,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -699,7 +696,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index aff762643..76e4b0b8e 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -303,7 +303,7 @@ type=ExeTracer
 eventq_index=0
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -312,7 +312,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -323,7 +323,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -395,9 +394,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -409,16 +408,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -430,23 +429,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -458,23 +457,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -486,9 +485,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -500,142 +499,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -647,9 +646,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -661,16 +660,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -682,12 +681,12 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -696,7 +695,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -707,7 +706,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -798,7 +796,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -807,7 +805,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -818,7 +816,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -862,7 +859,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index d0a6f1772..cc7bd2d63 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -149,7 +149,7 @@ instShiftAmt=2
 numThreads=1
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -158,7 +158,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=6
 prefetch_on_access=false
@@ -169,7 +169,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=16
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=IntDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList1.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IprAccess
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList
 [system.cpu.fuPool.FUList2.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList
 [system.cpu.fuPool.FUList3.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -311,187 +310,187 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys
 [system.cpu.fuPool.FUList4.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=9
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList20]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList21]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList22]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=5
+pipelined=true
 
 [system.cpu.fuPool.FUList4.opList23]
 type=OpDesc
 eventq_index=0
-issueLat=9
 opClass=FloatDiv
 opLat=9
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList24]
 type=OpDesc
 eventq_index=0
-issueLat=33
 opClass=FloatSqrt
 opLat=33
+pipelined=false
 
 [system.cpu.fuPool.FUList4.opList25]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -500,7 +499,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=1
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=2
 prefetch_on_access=false
@@ -511,7 +510,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -602,7 +600,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
@@ -611,7 +609,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=16
 prefetch_on_access=true
@@ -622,7 +620,6 @@ size=1048576
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=8
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -691,7 +688,7 @@ env=
 errout=cerr
 euid=100
 eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/arm/linux/hello
+executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 kvmInSE=false
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 5fb17fcaa..0e18c01bd 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -89,7 +89,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -100,7 +100,6 @@ size=262144
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -157,7 +156,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
@@ -166,7 +165,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -177,7 +176,6 @@ size=131072
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -268,7 +266,7 @@ sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
-type=BaseCache
+type=Cache
 children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
@@ -277,7 +275,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -288,7 +286,6 @@ size=2097152
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]