diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
| commit | 3c666083c6f5fecc38699a6f0c5f4f25b23e18c9 (patch) | |
| tree | e554e37e76714f9ae9c9faa07ef645db0f9a6d93 /tests/quick/se/00.hello/ref/arm | |
| parent | 8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (diff) | |
| download | gem5-3c666083c6f5fecc38699a6f0c5f4f25b23e18c9.tar.xz | |
ARM: Update stats for IT and conditional branch changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
15 files changed, 704 insertions, 704 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index e76d62054..5d5098bd1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -573,7 +573,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 762733a64..d9b6fdd69 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:35 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10389500 because target called exit() +Exiting @ tick 10303500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 3a90ce183..2d5ac9cf2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10389500 # Number of ticks simulated -final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10303500 # Number of ticks simulated +final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29724 # Simulator instruction rate (inst/s) -host_op_rate 37079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67113828 # Simulator tick rate (ticks/s) -host_mem_usage 225376 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 46836 # Simulator instruction rate (inst/s) +host_op_rate 58425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104878029 # Simulator tick rate (ticks/s) +host_mem_usage 222544 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_read 25664 # Number of bytes read from this memory system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 400 # Number of read requests responded to by this memory +system.physmem.num_reads 401 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -108,102 +108,102 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20780 # number of cpu cycles simulated +system.cpu.numCycles 20608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2550 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits +system.cpu.BPredUnit.lookups 2552 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2634 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2624 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available @@ -239,115 +239,115 @@ system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9138 # Type of FU issued -system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.FU_type_0::total 9165 # Type of FU issued +system.cpu.iq.rate 0.444730 # Inst issue rate system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3325 # number of memory reference insts executed -system.cpu.iew.exec_branches 1404 # Number of branches executed -system.cpu.iew.exec_stores 1195 # Number of stores executed -system.cpu.iew.exec_rate 0.415544 # Inst execution rate -system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3863 # num instructions producing a value -system.cpu.iew.wb_consumers 7813 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1406 # Number of branches executed +system.cpu.iew.exec_stores 1199 # Number of stores executed +system.cpu.iew.exec_rate 0.420565 # Inst execution rate +system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3874 # num instructions producing a value +system.cpu.iew.wb_consumers 7832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -360,61 +360,61 @@ system.cpu.commit.int_insts 4985 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22664 # The number of ROB reads -system.cpu.rob.rob_writes 24737 # The number of ROB writes -system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22629 # The number of ROB reads +system.cpu.rob.rob_writes 24771 # The number of ROB writes +system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39570 # number of integer regfile reads -system.cpu.int_regfile_writes 8020 # number of integer regfile writes +system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39716 # number of integer regfile reads +system.cpu.int_regfile_writes 8038 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16023 # number of misc regfile reads +system.cpu.misc_regfile_reads 16043 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use -system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use +system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits -system.cpu.icache.overall_hits::total 1663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits +system.cpu.icache.overall_hits::total 1665 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,52 +423,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use +system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits -system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits +system.cpu.dcache.overall_hits::total 2405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses @@ -479,38 +479,38 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,65 +537,65 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses -system.cpu.l2cache.overall_misses::total 404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses +system.cpu.l2cache.overall_misses::total 405 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -608,19 +608,19 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,41 +636,41 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 29d0ee1dd..e584370ea 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -514,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index cdeb6fd62..9bfa3671c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10389500 because target called exit() +Exiting @ tick 10303500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index b762714e2..c4c9274ca 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10389500 # Number of ticks simulated -final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10303500 # Number of ticks simulated +final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31505 # Simulator instruction rate (inst/s) -host_op_rate 39300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71135954 # Simulator tick rate (ticks/s) -host_mem_usage 225060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 48410 # Simulator instruction rate (inst/s) +host_op_rate 60388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108401694 # Simulator tick rate (ticks/s) +host_mem_usage 222284 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_read 25664 # Number of bytes read from this memory system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 400 # Number of read requests responded to by this memory +system.physmem.num_reads 401 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,102 +63,102 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20780 # number of cpu cycles simulated +system.cpu.numCycles 20608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2550 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits +system.cpu.BPredUnit.lookups 2552 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2634 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2624 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available @@ -194,115 +194,115 @@ system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9138 # Type of FU issued -system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.FU_type_0::total 9165 # Type of FU issued +system.cpu.iq.rate 0.444730 # Inst issue rate system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3325 # number of memory reference insts executed -system.cpu.iew.exec_branches 1404 # Number of branches executed -system.cpu.iew.exec_stores 1195 # Number of stores executed -system.cpu.iew.exec_rate 0.415544 # Inst execution rate -system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3863 # num instructions producing a value -system.cpu.iew.wb_consumers 7813 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1406 # Number of branches executed +system.cpu.iew.exec_stores 1199 # Number of stores executed +system.cpu.iew.exec_rate 0.420565 # Inst execution rate +system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3874 # num instructions producing a value +system.cpu.iew.wb_consumers 7832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -315,61 +315,61 @@ system.cpu.commit.int_insts 4985 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22664 # The number of ROB reads -system.cpu.rob.rob_writes 24737 # The number of ROB writes -system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22629 # The number of ROB reads +system.cpu.rob.rob_writes 24771 # The number of ROB writes +system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39570 # number of integer regfile reads -system.cpu.int_regfile_writes 8020 # number of integer regfile writes +system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39716 # number of integer regfile reads +system.cpu.int_regfile_writes 8038 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16023 # number of misc regfile reads +system.cpu.misc_regfile_reads 16043 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use -system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use +system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits -system.cpu.icache.overall_hits::total 1663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits +system.cpu.icache.overall_hits::total 1665 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,52 +378,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use +system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits -system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits +system.cpu.dcache.overall_hits::total 2405 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses @@ -434,38 +434,38 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -492,65 +492,65 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses -system.cpu.l2cache.overall_misses::total 404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses +system.cpu.l2cache.overall_misses::total 405 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -563,19 +563,19 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,41 +591,41 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1bb97fb57..305feda00 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -154,7 +154,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 708e8b4cb..38e35b911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:56 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 047a13c77..693c12922 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25080 # Simulator instruction rate (inst/s) -host_op_rate 31285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15673750 # Simulator tick rate (ticks/s) -host_mem_usage 214860 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 95261 # Simulator instruction rate (inst/s) +host_op_rate 118814 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59514762 # Simulator tick rate (ticks/s) +host_mem_usage 212272 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory @@ -117,7 +117,7 @@ system.cpu.committedOps 5739 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25237 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 85d2a6f4f..a6e23776e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index a7a548730..af4cba8f6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:33:45 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b76299081..ed3ee4578 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24562 # Simulator instruction rate (inst/s) -host_op_rate 30640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15350765 # Simulator tick rate (ticks/s) -host_mem_usage 214764 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 126142 # Simulator instruction rate (inst/s) +host_op_rate 157316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78793699 # Simulator tick rate (ticks/s) +host_mem_usage 212180 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 5739 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25237 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 50ec8fd07..92e235eb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -183,7 +183,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 25b5aeda6..976d6a78b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:15 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 16:34:06 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 4b008ff5c..2c4a7f677 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29458 # Simulator instruction rate (inst/s) -host_op_rate 36586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 169706423 # Simulator tick rate (ticks/s) -host_mem_usage 223936 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 140316 # Simulator instruction rate (inst/s) +host_op_rate 174230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 807994403 # Simulator tick rate (ticks/s) +host_mem_usage 221092 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4574 # Number of instructions simulated sim_ops 5682 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22400 # Number of bytes read from this memory @@ -71,7 +71,7 @@ system.cpu.committedOps 5682 # Nu system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls system.cpu.num_int_insts 4985 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 28701 # number of times the integer registers were read |