diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 14:14:36 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 14:14:36 +0100 |
| commit | 1d933447fc62de67db938970a8308ac47189fd96 (patch) | |
| tree | df7f389eeae7916c3a58082644d6929bf0e94280 /tests/quick/se/00.hello/ref/arm | |
| parent | 660fbd543f7c84dec81cd17bdb4ff08f954aec77 (diff) | |
| download | gem5-1d933447fc62de67db938970a8308ac47189fd96.tar.xz | |
stats: Update to match ARM ISA changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
9 files changed, 41 insertions, 33 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 3c6706440..97296d3da 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. @@ -9,4 +11,4 @@ command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/li Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 17170000 because target called exit() +Exiting @ tick 17232500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 203ef51d3..9149a2fa0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37479 # Simulator instruction rate (inst/s) -host_op_rate 43886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140595410 # Simulator tick rate (ticks/s) -host_mem_usage 265936 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 74741 # Simulator instruction rate (inst/s) +host_op_rate 87520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 280399381 # Simulator tick rate (ticks/s) +host_mem_usage 309668 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -554,7 +554,7 @@ system.cpu.rename.IQFullEvents 166 # Nu system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52722 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed @@ -571,7 +571,7 @@ system.cpu.iq.iqNonSpecInstsAdded 43 # Nu system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12413 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle @@ -791,7 +791,7 @@ system.cpu.int_regfile_writes 4270 # nu system.cpu.fp_regfile_reads 32 # number of floating regfile reads system.cpu.cc_regfile_reads 27801 # number of cc regfile reads system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3010 # number of misc regfile reads +system.cpu.misc_regfile_reads 2978 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 5c8d62c82..e4ae04024 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. @@ -9,4 +11,4 @@ command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/li Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18741000 because target called exit() +Exiting @ tick 18821000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 17fbc7c06..d093f5feb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22479 # Simulator instruction rate (inst/s) -host_op_rate 26323 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92110547 # Simulator tick rate (ticks/s) -host_mem_usage 261716 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 77535 # Simulator instruction rate (inst/s) +host_op_rate 90790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 317684946 # Simulator tick rate (ticks/s) +host_mem_usage 305172 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -435,7 +435,7 @@ system.cpu.rename.IQFullEvents 1 # Nu system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41158 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed @@ -672,7 +672,7 @@ system.cpu.int_regfile_writes 3787 # nu system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.cc_regfile_reads 24229 # number of cc regfile reads system.cpu.cc_regfile_writes 2921 # number of cc regfile writes -system.cpu.misc_regfile_reads 2578 # number of misc regfile reads +system.cpu.misc_regfile_reads 2562 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index bcfa49270..12cffc971 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274500 # Simulator instruction rate (inst/s) -host_op_rate 321069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 160714630 # Simulator tick rate (ticks/s) -host_mem_usage 254660 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 555825 # Simulator instruction rate (inst/s) +host_op_rate 650110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 325439975 # Simulator tick rate (ticks/s) +host_mem_usage 298640 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -283,7 +283,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7607 # number of times the integer registers were read +system.cpu.num_int_register_reads 7572 # number of times the integer registers were read system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 994e2e646..98eb95060 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 6f1efaf21..80bb8332d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 363981 # Simulator instruction rate (inst/s) -host_op_rate 425522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 212904964 # Simulator tick rate (ticks/s) -host_mem_usage 254404 # Number of bytes of host memory used +host_inst_rate 589705 # Simulator instruction rate (inst/s) +host_op_rate 689852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345334530 # Simulator tick rate (ticks/s) +host_mem_usage 297616 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated @@ -164,7 +164,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7607 # number of times the integer registers were read +system.cpu.num_int_register_reads 7572 # number of times the integer registers were read system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 1bcd9c702..daa769407 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index e99784abb..78aca14dc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 343617 # Simulator instruction rate (inst/s) -host_op_rate 400476 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2123290642 # Simulator tick rate (ticks/s) -host_mem_usage 263372 # Number of bytes of host memory used +host_inst_rate 311400 # Simulator instruction rate (inst/s) +host_op_rate 363255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1927478424 # Simulator tick rate (ticks/s) +host_mem_usage 306584 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -158,7 +158,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls system.cpu.num_int_insts 4624 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7573 # number of times the integer registers were read +system.cpu.num_int_register_reads 7538 # number of times the integer registers were read system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |