diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/quick/se/00.hello/ref/mips/linux/inorder-timing | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/inorder-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt | 490 |
1 files changed, 245 insertions, 245 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 8aae2e3f0..02dd2c613 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19373000 # Number of ticks simulated -final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18578000 # Number of ticks simulated +final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54522 # Simulator instruction rate (inst/s) -host_op_rate 54510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181593348 # Simulator tick rate (ticks/s) -host_mem_usage 216696 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 97793 # Simulator instruction rate (inst/s) +host_op_rate 97754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 312246493 # Simulator tick rate (ticks/s) +host_mem_usage 216964 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19298000 # Total gap between requests +system.physmem.totGap 18503000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2404453 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests +system.physmem.totQLat 2353954 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests system.physmem.totBusLat 1820000 # Total cycles spent in databus access -system.physmem.totBankLat 8470000 # Total cycles spent in bank access -system.physmem.avgQLat 5284.51 # Average queueing delay per request -system.physmem.avgBankLat 18615.38 # Average bank access latency per request +system.physmem.totBankLat 8484000 # Total cycles spent in bank access +system.physmem.avgQLat 5173.53 # Average queueing delay per request +system.physmem.avgBankLat 18646.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27899.90 # Average memory access latency -system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27819.68 # Average memory access latency +system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.39 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.66 # Average read queue length over time +system.physmem.busUtil 9.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.68 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42413.19 # Average gap between requests +system.physmem.avgGap 40665.93 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,7 +204,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 38747 # number of cpu cycles simulated +system.cpu.numCycles 37157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -217,13 +217,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2235 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). @@ -234,12 +234,12 @@ system.cpu.execution_unit.executions 3144 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. -system.cpu.activity 13.897850 # Percentage of cycles cpu is active +system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5375 # Number of cycles cpu stages are processed. +system.cpu.activity 14.465646 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -251,144 +251,144 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads +system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use +system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits system.cpu.icache.overall_hits::total 410 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses +system.cpu.icache.overall_misses::total 346 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.457672 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.457672 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 25 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use -system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use +system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021834 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 762 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1834 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1834 # number of overall hits -system.cpu.dcache.overall_hits::total 1834 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 163 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 254 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses -system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8188000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13685500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13685500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 89.860913 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits +system.cpu.dcache.overall_hits::total 1644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses +system.cpu.dcache.overall_misses::total 444 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14658500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20247500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -397,38 +397,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078246 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078246 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.176216 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.176216 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 112 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 112 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -437,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -453,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -490,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -523,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -575,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |