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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
tree | 64b85031cb791a21af6059778384d358d992b817 /tests/quick/se/00.hello/ref/mips/linux/inorder-timing | |
parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/inorder-timing')
3 files changed, 43 insertions, 49 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index df7d00601..0b4834ee5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,18 +31,13 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 +children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload activity=0 +branchPred=system.cpu.branchPred cachePorts=2 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 cpu_id=0 -defer_registration=false div16Latency=1 div16RepeatRate=1 div24Latency=1 @@ -57,17 +53,9 @@ dtb=system.cpu.dtb fetchBuffSize=4 function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -76,11 +64,11 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 stageTracing=false stageWidth=4 +switched_out=false system=system threadModel=SMT tracer=system.cpu.tracer @@ -88,6 +76,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -95,21 +101,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -126,21 +127,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -165,21 +161,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -206,7 +197,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 75053b5ab..25f28ceed 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:08:52 -gem5 started Oct 30 2012 13:57:29 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 15:16:48 +gem5 started Jan 23 2013 15:16:55 +gem5 executing on ribera.cs.wisc.edu command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 5bb87ba63..7f0e6e36f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18578000 # Number of ticks simulated final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59954 # Simulator instruction rate (inst/s) -host_op_rate 59945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191522194 # Simulator tick rate (ticks/s) -host_mem_usage 214528 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 49489 # Simulator instruction rate (inst/s) +host_op_rate 49481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158085302 # Simulator tick rate (ticks/s) +host_mem_usage 270352 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 40665.93 # Average gap between requests +system.cpu.branchPred.lookups 1154 # Number of BP lookups +system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups +system.cpu.branchPred.BTBHits 336 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -207,14 +216,6 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 37157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1154 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 858 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 877 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 336 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 38.312429 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File |