diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/se/00.hello/ref/mips/linux/inorder-timing | |
parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/inorder-timing')
3 files changed, 259 insertions, 180 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 1ccb30b9c..600677fb9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 677598e87..9f59be0ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:29 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:30 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 78172e7b6..6cd55fbff 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000020 # Nu sim_ticks 19785000 # Number of ticks simulated final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71616 # Simulator instruction rate (inst/s) -host_tick_rate 243111037 # Simulator tick rate (ticks/s) -host_mem_usage 208328 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101976 # Simulator instruction rate (inst/s) +host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346042004 # Simulator tick rate (ticks/s) +host_mem_usage 210372 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,9 +56,10 @@ system.cpu.comNops 657 # Nu system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads @@ -110,26 +113,39 @@ system.cpu.icache.total_refs 443 # To system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits -system.cpu.icache.demand_hits 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits 443 # number of overall hits -system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses -system.cpu.icache.demand_misses 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits +system.cpu.icache.overall_hits::total 443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses +system.cpu.icache.overall_misses::total 341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -138,27 +154,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use @@ -166,32 +185,49 @@ system.cpu.dcache.total_refs 1838 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits -system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses -system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits +system.cpu.dcache.overall_hits::total 1838 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.dcache.overall_misses::total 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +236,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use @@ -233,31 +275,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.l2cache.overall_misses::total 455 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,30 +341,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |