bp: fix up stats for changes to branch predictor

2 files changed, 152 insertions, 152 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 9f59be0ce..e34fa5006 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:07:32
-gem5 started Feb 11 2012 13:54:30
+gem5 compiled Feb 12 2012 17:16:48
+gem5 started Feb 12 2012 18:16:47
 gem5 executing on zizzer
 command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 19785000 because target called exit()
+Exiting @ tick 19775000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 6cd55fbff..e8bd2f84c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19785000                       # Number of ticks simulated
-final_tick                                   19785000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19775000                       # Number of ticks simulated
+final_tick                                   19775000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 101976                       # Simulator instruction rate (inst/s)
-host_op_rate                                   101944                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              346042004                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210372                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 108846                       # Simulator instruction rate (inst/s)
+host_op_rate                                   108810                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              369151681                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210376                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
@@ -17,9 +17,9 @@ system.physmem.bytes_written                        0                       # Nu
 system.physmem.num_reads                          455                       # Number of read requests responded to by this memory
 system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     1471822087                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1025423300                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    1471822087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                     1472566372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1025941846                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    1472566372                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -39,16 +39,16 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            39571                       # number of cpu cycles simulated
+system.cpu.numCycles                            39551                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9159                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9142                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             403                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           34166                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             5405                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         13.658993                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             404                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           34183                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             5368                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         13.572350                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1164                       # Number of Load instructions committed
 system.cpu.comStores                              925                       # Number of Store instructions committed
 system.cpu.comBranches                            916                       # Number of Branches instructions committed
@@ -60,92 +60,92 @@ system.cpu.committedInsts                        5827                       # Nu
 system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.790973                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               6.787541                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.790973                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.147254                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         6.787541                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.147329                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.147254                       # IPC: Total IPC of All Threads
-system.cpu.branch_predictor.lookups              1185                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted          896                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect          611                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           1035                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits               443                       # Number of BTB hits
+system.cpu.ipc_total                         0.147329                       # IPC: Total IPC of All Threads
+system.cpu.branch_predictor.lookups              1152                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted          851                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect          605                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups            867                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits               309                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect           32                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       42.801932                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken          536                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken          649                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5108                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct       35.640138                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken          402                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken          750                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5104                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites         3408                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         8516                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         8512                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           1344                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       2228                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect          317                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          285                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted            602                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted               314                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     65.720524                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions             3132                       # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards           1330                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       2238                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect          262                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect          334                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted            596                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted               320                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     65.065502                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions             3155                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
-system.cpu.stage0.idleCycles                    35846                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      3725                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                9.413459                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    36723                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      2848                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                7.197190                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    36778                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      2793                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                7.058199                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    38328                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.idleCycles                    35911                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      3640                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization                9.203307                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    36722                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      2829                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                7.152790                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    36760                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2791                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                7.056712                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    38308                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1243                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.141189                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    36666                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      2905                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                7.341235                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization                3.142778                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    36647                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      2904                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                7.342419                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                148.138598                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      443                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                148.175887                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      411                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   1.388715                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   1.288401                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     148.138598                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.072333                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.072333                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst          443                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             443                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           443                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              443                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          443                       # number of overall hits
-system.cpu.icache.overall_hits::total             443                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          341                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           341                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          341                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            341                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          341                       # number of overall misses
-system.cpu.icache.overall_misses::total           341                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19027500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19027500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19027500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19027500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19027500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19027500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          784                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          784                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          784                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          784                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          784                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          784                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.434949                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.434949                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.434949                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     148.175887                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.072352                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.072352                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          411                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             411                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           411                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              411                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          411                       # number of overall hits
+system.cpu.icache.overall_hits::total             411                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          343                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           343                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          343                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            343                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          343                       # number of overall misses
+system.cpu.icache.overall_misses::total           343                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19128500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19128500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19128500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19128500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19128500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19128500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          754                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          754                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          754                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          754                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          754                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          754                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.454907                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.454907                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.454907                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -154,40 +154,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           22                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           24                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           24                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16952500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16952500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16952500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16952500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16952500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16952500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16951500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16951500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16951500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16951500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16951500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16951500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 89.732679                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 89.746602                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1838                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.318841                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      89.732679                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021907                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021907                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      89.746602                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021911                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021911                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1075                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1075                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          763                       # number of WriteReq hits
@@ -206,12 +206,12 @@ system.cpu.dcache.overall_misses::cpu.data          251                       #
 system.cpu.dcache.overall_misses::total           251                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data      5072500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      5072500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      8912000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8912000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13984500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13984500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13984500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13984500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8910500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8910500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13983000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13983000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13983000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13983000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -225,9 +225,9 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.175135
 system.cpu.dcache.demand_miss_rate::cpu.data     0.120153                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.120153                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -254,32 +254,32 @@ system.cpu.dcache.overall_mshr_misses::cpu.data          138
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4702500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      4702500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2746000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2746000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7448500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7448500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7448500                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2745500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2745500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7448000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               205.469583                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               205.517886                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    149.779235                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     55.690348                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004571                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    149.817885                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     55.700002                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004572                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.001700                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006270                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006272                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -297,17 +297,17 @@ system.cpu.l2cache.demand_misses::total           455                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16585500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16585000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4585000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     21170500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2682500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2682500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16585500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7267500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23853000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16585500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7267500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23853000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     21170000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2682000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2682000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16585000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7267000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23852000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16585000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7267000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23852000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -326,13 +326,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked