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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
commit | d7c083864c85c3ab24b40fc85ef3cae8031c5912 (patch) | |
tree | ae575d831de5d67596ca3aae5e87a71f9c9fd1cd /tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout | |
parent | 9b4249410ec18cac9df2c7e9c0a4a6ce5459233d (diff) | |
download | gem5-d7c083864c85c3ab24b40fc85ef3cae8031c5912.tar.xz |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout')
-rwxr-xr-x | tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 811ca2575..fea443199 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:42:39 -gem5 started Mar 13 2016 22:47:14 -gem5 executing on phenom, pid 19880 +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29859 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second |