stats: update stats for insts/ops and master id changes

3 files changed, 260 insertions, 178 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 508c3cad4..00305a8e7 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index eb1e6f70f..afa267678 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:41
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:39
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index e49d82dd9..9ff42644b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12272500                       # Number of ticks simulated
 final_tick                                   12272500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65845                       # Simulator instruction rate (inst/s)
-host_tick_rate                              156294886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208908                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  97350                       # Simulator instruction rate (inst/s)
+host_op_rate                                    97317                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              230983195                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211060                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
+sim_ops                                          5169                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30400                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  21312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -255,6 +257,7 @@ system.cpu.iew.wb_rate                       0.289986                       # in
 system.cpu.iew.wb_fanout                     0.698936                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5826                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            4197                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               357                       # The number of times a branch was mispredicted
@@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        11871                       # Number of insts commited each cycle
-system.cpu.commit.count                          5826                       # Number of instructions committed
+system.cpu.commit.committedInsts                 5826                       # Number of instructions committed
+system.cpu.commit.committedOps                   5826                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2089                       # Number of memory references committed
 system.cpu.commit.loads                          1164                       # Number of loads committed
@@ -291,6 +295,7 @@ system.cpu.rob.rob_writes                       20794                       # Th
 system.cpu.timesIdled                             251                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           11938                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
+system.cpu.committedOps                          5169                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
 system.cpu.cpi                               4.748694                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         4.748694                       # CPI: Total CPI of All Threads
@@ -307,26 +312,39 @@ system.cpu.icache.total_refs                     1363                       # To
 system.cpu.icache.sampled_refs                    336                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   4.056548                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            161.224498                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.078723                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1363                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1363                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1363                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  418                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   418                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  418                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15148000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15148000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15148000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1781                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1781                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1781                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.234700                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.234700                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.234700                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36239.234450                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36239.234450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36239.234450                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     161.224498                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.078723                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.078723                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1363                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1363                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1363                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1363                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1363                       # number of overall hits
+system.cpu.icache.overall_hits::total            1363                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          418                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           418                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          418                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            418                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          418                       # number of overall misses
+system.cpu.icache.overall_misses::total           418                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15148000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15148000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15148000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15148000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15148000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15148000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1781                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1781                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1781                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1781                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1781                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1781                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.234700                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.234700                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.234700                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -335,27 +353,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                82                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 82                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                82                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             336                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              336                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             336                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11784000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     11784000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     11784000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.188658                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.188658                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.188658                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           82                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           82                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           82                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           82                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           82                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          336                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          336                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          336                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          336                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11784000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11784000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11784000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11784000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11784000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11784000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 92.121984                       # Cycle average of tags in use
@@ -363,32 +384,49 @@ system.cpu.dcache.total_refs                     2380                       # To
 system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  16.760563                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             92.121984                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.022491                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1802                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   578                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2380                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2380                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  133                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 347                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   480                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  480                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        4767500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      11508000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        16275500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       16275500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1935                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2860                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2860                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.068734                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.375135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.167832                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.167832                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33907.291667                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33907.291667                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      92.121984                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.022491                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.022491                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          578                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            578                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2380                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2380                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2380                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2380                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          347                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          347                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          480                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
+system.cpu.dcache.overall_misses::total           480                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4767500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4767500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     11508000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     11508000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16275500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16275500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16275500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16275500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1935                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1935                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2860                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2860                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2860                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2860                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068734                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.375135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.167832                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.167832                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -397,32 +435,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                42                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              296                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                338                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               338                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              91                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             142                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      3272000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1836000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5108000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.047028                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.049650                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.049650                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        36000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          338                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          338                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          338                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          338                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1836000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1836000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5108000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5108000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.047028                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.049650                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.049650                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        36000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               221.521956                       # Cycle average of tags in use
@@ -430,31 +474,64 @@ system.cpu.l2cache.total_refs                       3                       # To
 system.cpu.l2cache.sampled_refs                   424                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.007075                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           221.521956                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006760                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 424                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  475                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 475                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14561000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1760500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16321500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16321500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               427                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                478                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               478                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.992974                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.993724                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.993724                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34361.052632                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34361.052632                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    163.434563                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     58.087393                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004988                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001773                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006760                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          333                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          424                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          333                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           475                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          333                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          475                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11418500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3142500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14561000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1760500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1760500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11418500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4903000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16321500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11418500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4903000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16321500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          336                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          427                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          336                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          478                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          336                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          478                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991071                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991071                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991071                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -463,30 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             475                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            475                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13198000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1598500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14796500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.992974                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.993724                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.993724                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          333                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          424                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          333                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          475                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          333                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          475                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10340500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2857500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13198000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1598500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1598500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10340500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10340500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4456000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14796500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------