diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-10 12:44:03 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-10 12:44:03 -0500 |
commit | 5cdf221d8ce3f5b983672f26346aefc21b37a752 (patch) | |
tree | ac039244b78f69bee1d0dea82e48827fba97fe3c /tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini | |
parent | c5bf1390aa129fefa7102e2de2998c0e6b09b5b0 (diff) | |
download | gem5-5cdf221d8ce3f5b983672f26346aefc21b37a752.tar.xz |
Regression: Updates due to changes to Ruby memory controller
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini')
-rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 42e36b24c..6ebb273d9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000 type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -118,9 +118,9 @@ bank_busy_time=11 bank_queue_size=12 banks_per_rank=8 basic_bus_busy_time=2 +clock=3 dimm_bit_0=12 dimms_per_channel=2 -mem_bus_cycle_multiplier=10 mem_ctl_latency=12 mem_fixed_delay=0 mem_random_arbitrate=0 @@ -129,6 +129,7 @@ rank_rank_delay=1 ranks_per_dimm=2 read_write_delay=2 refresh_period=1560 +ruby_system=system.ruby tFaw=0 version=0 @@ -165,6 +166,7 @@ tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer access_phys_mem=true +clock=1 dcache=system.l1_cntrl0.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.cacheMemory @@ -180,6 +182,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory +clock=1 conf_table_reported=false file= in_addr_map=true @@ -281,6 +284,7 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true +clock=1 ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true |