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authorAndreas Hansson <andreas.hansson@arm.com>2012-09-10 11:57:47 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-09-10 11:57:47 -0400
commit0b1108c7a3a71bc994e9af00b992c2c693c65e97 (patch)
treeeead52c8d8c5bc2db64033ef63760a073077bf35 /tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby
parent9e0edbcea8d14446487f13f56b65c669ba580673 (diff)
downloadgem5-0b1108c7a3a71bc994e9af00b992c2c693c65e97.tar.xz
Ruby: Bump the stats after recent memory controller changes
This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby')
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt40
1 files changed, 20 insertions, 20 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index a8b1b136a..461dc447d 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000293 # Number of seconds simulated
-sim_ticks 292960 # Number of ticks simulated
-final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000125 # Number of seconds simulated
+sim_ticks 125334 # Number of ticks simulated
+final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 57090 # Simulator instruction rate (inst/s)
-host_op_rate 57080 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2875747 # Simulator tick rate (ticks/s)
-host_mem_usage 235412 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 39466 # Simulator instruction rate (inst/s)
+host_op_rate 39462 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 850593 # Simulator tick rate (ticks/s)
+host_mem_usage 235544 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
@@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.data 1163 # Nu
system.physmem.num_reads::total 6978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory
system.physmem.num_writes::total 925 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 79396505 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 14930366 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 94326871 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 79396505 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 79396505 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 12486346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 12486346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 79396505 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 27416712 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 106813217 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 185584119 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 34898751 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 220482870 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 185584119 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 185584119 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 29186015 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 29186015 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 185584119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 64084766 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 249668885 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -58,7 +58,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 292960 # number of cpu cycles simulated
+system.cpu.numCycles 125334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5814 # Number of instructions committed
@@ -77,7 +77,7 @@ system.cpu.num_mem_refs 2089 # nu
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 292960 # Number of busy cycles
+system.cpu.num_busy_cycles 125334 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles