diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby')
| -rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 410 |
1 files changed, 205 insertions, 205 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 8476aa73a..c6923a4b0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000115 # Number of seconds simulated -sim_ticks 115467 # Number of ticks simulated -final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 115089 # Number of ticks simulated +final_tick 115089 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66709 # Simulator instruction rate (inst/s) -host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1369179 # Simulator tick rate (ticks/s) -host_mem_usage 449556 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 64252 # Simulator instruction rate (inst/s) +host_op_rate 64242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1314462 # Simulator tick rate (ticks/s) +host_mem_usage 449728 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1632684270 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1632684270 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 58496 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 35584 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 59392 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 556 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 513 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 78 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 115 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 33 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 245 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 98 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 186 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115396 # Total gap between requests +system.mem_ctrls.totGap 115018 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 914 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,26 +135,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -184,89 +184,89 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12340 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 339.965015 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.922152 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.777927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 88 25.66% 25.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 98 28.57% 54.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 42 12.24% 66.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 32 9.33% 75.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 4.66% 80.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.79% 84.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.33% 86.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.46% 88.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 11.95% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 343 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 56 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.125000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.967614 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.737368 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.57% 3.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 19 33.93% 37.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 27 48.21% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 7 12.50% 98.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.79% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 56 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 56 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.571429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.541189 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.041976 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 41 73.21% 73.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 5.36% 78.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 8 14.29% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 5.36% 98.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.79% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 56 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12397 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29763 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4570 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.56 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.56 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 508.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 516.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 817.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 815.23 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.00 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.03 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.30 # Average gap between requests -system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.10 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 631 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 861 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 69.04 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.18 # Average gap between requests +system.mem_ctrls.pageHitRate 79.91 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 544320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 302400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1522560 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1202688 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.actBackEnergy 49529808 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 22111200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 82332816 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 753.521892 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 36376 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 69262 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1988280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1104600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9397440 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 8076672 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.actBackEnergy 74119608 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 541200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102347640 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 936.700469 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105142 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -288,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115467 # number of cpu cycles simulated +system.cpu.numCycles 115089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -307,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115467 # Number of busy cycles +system.cpu.num_busy_cycles 115089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -362,10 +362,10 @@ system.ruby.outstanding_req_hist::total 7659 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.077958 -system.ruby.latency_hist::gmean 5.242569 -system.ruby.latency_hist::stdev 26.858459 -system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 14.028598 +system.ruby.latency_hist::gmean 5.234161 +system.ruby.latency_hist::stdev 27.167008 +system.ruby.latency_hist | 7344 95.90% 95.90% | 261 3.41% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 9 0.12% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 7658 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -377,17 +377,17 @@ system.ruby.hit_latency_hist::total 6188 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.710884 -system.ruby.miss_latency_hist::gmean 54.957755 -system.ruby.miss_latency_hist::stdev 32.665540 -system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 60.453741 +system.ruby.miss_latency_hist::gmean 54.500138 +system.ruby.miss_latency_hist::stdev 34.320124 +system.ruby.miss_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1470 system.ruby.Directory.incomplete_times 1469 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.percent_links_utilized 6.377673 system.ruby.network.routers0.msg_count.Control::2 1470 system.ruby.network.routers0.msg_count.Data::2 1466 system.ruby.network.routers0.msg_count.Response_Data::4 1470 @@ -396,7 +396,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760 system.ruby.network.routers0.msg_bytes.Data::2 105552 system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.percent_links_utilized 6.377673 system.ruby.network.routers1.msg_count.Control::2 1470 system.ruby.network.routers1.msg_count.Data::2 1466 system.ruby.network.routers1.msg_count.Response_Data::4 1470 @@ -405,7 +405,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760 system.ruby.network.routers1.msg_bytes.Data::2 105552 system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.percent_links_utilized 6.377673 system.ruby.network.routers2.msg_count.Control::2 1470 system.ruby.network.routers2.msg_count.Data::2 1466 system.ruby.network.routers2.msg_count.Response_Data::4 1470 @@ -422,32 +422,32 @@ system.ruby.network.msg_byte.Control 35280 system.ruby.network.msg_byte.Data 316656 system.ruby.network.msg_byte.Response_Data 317520 system.ruby.network.msg_byte.Writeback_Control 35184 -system.ruby.network.routers0.throttle0.link_utilization 6.363723 +system.ruby.network.routers0.throttle0.link_utilization 6.384624 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.349866 +system.ruby.network.routers0.throttle1.link_utilization 6.370722 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.349866 +system.ruby.network.routers1.throttle0.link_utilization 6.370722 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.363723 +system.ruby.network.routers1.throttle1.link_utilization 6.384624 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.363723 +system.ruby.network.routers2.throttle0.link_utilization 6.384624 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.349866 +system.ruby.network.routers2.throttle1.link_utilization 6.370722 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -462,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.492049 -system.ruby.LD.latency_hist::gmean 16.147834 -system.ruby.LD.latency_hist::stdev 37.303839 -system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% +system.ruby.LD.latency_hist::mean 35.838339 +system.ruby.LD.latency_hist::gmean 16.062923 +system.ruby.LD.latency_hist::stdev 41.117345 +system.ruby.LD.latency_hist | 998 88.16% 88.16% | 109 9.63% 97.79% | 13 1.15% 98.94% | 2 0.18% 99.12% | 7 0.62% 99.73% | 3 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -477,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.143928 -system.ruby.LD.miss_latency_hist::gmean 52.206801 -system.ruby.LD.miss_latency_hist::stdev 33.349415 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.731634 +system.ruby.LD.miss_latency_hist::gmean 51.741753 +system.ruby.LD.miss_latency_hist::stdev 39.915394 +system.ruby.LD.miss_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 667 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 14.748058 -system.ruby.ST.latency_hist::gmean 5.824702 -system.ruby.ST.latency_hist::stdev 24.783906 -system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.653718 +system.ruby.ST.latency_hist::gmean 5.820052 +system.ruby.ST.latency_hist::stdev 24.674998 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 188 20.87% 96.78% | 26 2.89% 99.67% | 0 0.00% 99.67% | 0 0.00% 99.67% | 1 0.11% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -503,18 +503,18 @@ system.ruby.ST.hit_latency_hist::total 684 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 51.778802 -system.ruby.ST.miss_latency_hist::gmean 47.157588 -system.ruby.ST.miss_latency_hist::stdev 27.288529 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.387097 +system.ruby.ST.miss_latency_hist::gmean 47.001474 +system.ruby.ST.miss_latency_hist::stdev 27.408897 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.miss_latency_hist::total 217 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::bucket_size 32 +system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.661156 -system.ruby.IFETCH.latency_hist::gmean 4.110524 -system.ruby.IFETCH.latency_hist::stdev 22.183687 -system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.539378 +system.ruby.IFETCH.latency_hist::gmean 4.106431 +system.ruby.IFETCH.latency_hist::stdev 21.247440 +system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 435 7.73% 97.32% | 121 2.15% 99.47% | 5 0.09% 99.56% | 8 0.14% 99.70% | 15 0.27% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -523,21 +523,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5039 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 66.940273 -system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 -system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 -system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.771331 +system.ruby.IFETCH.miss_latency_hist::gmean 61.076979 +system.ruby.IFETCH.miss_latency_hist::stdev 28.360902 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 -system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.453741 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.500138 +system.ruby.Directory.miss_mach_latency_hist::stdev 34.320124 +system.ruby.Directory.miss_mach_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -565,29 +565,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.731634 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 51.741753 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 39.915394 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.387097 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.001474 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.408897 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.771331 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.076979 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.360902 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% |