Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 654ee7d3b..b337ea793 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000033                       # Number of seconds simulated
-sim_ticks                                    33399000                       # Number of ticks simulated
-final_tick                                   33399000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000032                       # Number of seconds simulated
+sim_ticks                                    31633000                       # Number of ticks simulated
+final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 212162                       # Simulator instruction rate (inst/s)
-host_op_rate                                   212025                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1217250605                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223376                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 284864                       # Simulator instruction rate (inst/s)
+host_op_rate                                   284628                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1547353604                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219460                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            576783736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            264439055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               841222791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       576783736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          576783736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           576783736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           264439055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              841222791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            608984289                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            279202099                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               888186388                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       608984289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          608984289                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           608984289                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           279202099                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              888186388                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,7 +46,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            66798                       # number of cpu cycles simulated
+system.cpu.numCycles                            63266                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5814                       # Number of instructions committed
@@ -65,18 +65,18 @@ system.cpu.num_mem_refs                          2089                       # nu
 system.cpu.num_load_insts                        1163                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      66798                       # Number of busy cycles
+system.cpu.num_busy_cycles                      63266                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                133.141027                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                132.545353                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5513                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.194719                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     133.141027                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.065010                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.065010                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     132.545353                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.064719                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.064719                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
@@ -89,12 +89,12 @@ system.cpu.icache.demand_misses::cpu.inst          303                       # n
 system.cpu.icache.demand_misses::total            303                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          303                       # number of overall misses
 system.cpu.icache.overall_misses::total           303                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16884000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16884000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16884000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16884000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16884000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16884000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16581000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16581000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16581000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16581000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16581000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16581000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         5816                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         5816                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         5816                       # number of demand (read+write) accesses
@@ -107,12 +107,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.052098
 system.cpu.icache.demand_miss_rate::total     0.052098                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.052098                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.052098                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55722.772277                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55722.772277                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54722.772277                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54722.772277                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.742269                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 87.492114                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1950                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  14.130435                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.742269                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021421                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021421                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      87.492114                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021360                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
@@ -171,14 +171,14 @@ system.cpu.dcache.demand_misses::cpu.data          138                       # n
 system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4872000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4872000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2856000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2856000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4785000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4785000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2805000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2805000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -195,14 +195,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.066092
 system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.881290                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               188.114191                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    134.495649                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     54.385641                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004104                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001660                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005764                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    133.890657                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.223533                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004086                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001655                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005741                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits