stats: Update stats for syscall emulation Linux kernel changes.

1 files changed, 93 insertions, 93 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index eb8915cb4..654ee7d3b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000033                       # Number of seconds simulated
-sim_ticks                                    33413000                       # Number of ticks simulated
-final_tick                                   33413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    33399000                       # Number of ticks simulated
+final_tick                                   33399000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168189                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168105                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              963489284                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219036                       # Number of bytes of host memory used
+host_inst_rate                                 212162                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212025                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1217250605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223376                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                        5827                       # Number of instructions simulated
-sim_ops                                          5827                       # Number of ops (including micro ops) simulated
+sim_insts                                        5814                       # Number of instructions simulated
+sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28096                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            576542064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            264328255                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               840870320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       576542064                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          576542064                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           576542064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           264328255                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              840870320                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            576783736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            264439055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               841222791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       576783736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          576783736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           576783736                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           264439055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              841222791                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,43 +46,43 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            66826                       # number of cpu cycles simulated
+system.cpu.numCycles                            66798                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5827                       # Number of instructions committed
-system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.committedInsts                        5814                       # Number of instructions committed
+system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         5113                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7300                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2089                       # number of memory refs
+system.cpu.num_load_insts                        1163                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      66826                       # Number of busy cycles
+system.cpu.num_busy_cycles                      66798                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                133.092783                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     5526                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                133.141027                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     5513                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  18.237624                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  18.194719                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     133.092783                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.064987                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.064987                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         5526                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5526                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5526                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5526                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5526                       # number of overall hits
-system.cpu.icache.overall_hits::total            5526                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     133.141027                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.065010                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.065010                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5513                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5513                       # number of overall hits
+system.cpu.icache.overall_hits::total            5513                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          303                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           303                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          303                       # number of demand (read+write) misses
@@ -95,18 +95,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     16884000
 system.cpu.icache.demand_miss_latency::total     16884000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     16884000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     16884000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5829                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5829                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5829                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5829                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.051981                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.051981                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.051981                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.051981                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.051981                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.051981                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         5816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5816                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5816                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5816                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5816                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052098                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.052098                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.052098                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.052098                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.052098                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.052098                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
@@ -133,12 +133,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15975000
 system.cpu.icache.demand_mshr_miss_latency::total     15975000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15975000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     15975000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.051981                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.051981                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.051981                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.052098                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.052098                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
@@ -147,22 +147,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.717237                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1951                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 87.742269                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1950                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  14.137681                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.130435                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.717237                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021415                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021415                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1077                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1077                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      87.742269                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021421                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021421                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1951                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1951                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1951                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1951                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1950                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1950                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1950                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1950                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
@@ -179,22 +179,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7728000
 system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074742                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.074742                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074807                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074807                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.066060                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.066060                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.066060                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.066060                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000
 system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.818071                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               188.881290                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    134.446837                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     54.371234                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004103                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001659                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005762                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    134.495649                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.385641                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004104                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001660                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005764                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits