regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 140 insertions, 145 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 5e0921373..050099df0 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
-clock=1
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
 memories=system.physmem
 num_work_ids=16
 readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
 size=262144
-subblock_size=0
 system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
@@ -92,23 +90,18 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
 size=131072
-subblock_size=0
 system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
@@ -117,6 +110,11 @@ mem_side=system.cpu.toL2Bus.slave[0]
 [system.cpu.interrupts]
 type=MipsInterrupts
 
+[system.cpu.isa]
+type=MipsISA
+num_threads=1
+num_vpes=1
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -124,25 +122,20 @@ size=64
 [system.cpu.l2cache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
 is_top_level=false
 max_miss_count=0
-mshrs=10
+mshrs=20
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
 size=2097152
-subblock_size=0
 system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
@@ -151,10 +144,10 @@ mem_side=system.membus.slave[1]
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=1000
+clock=500
 header_cycles=1
 use_default_range=false
-width=8
+width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -193,7 +186,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1
+clock=1000
 conf_table_reported=false
 in_addr_map=true
 latency=30000
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 15c5cb118..3cdc50c15 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 13 2012 17:00:38
-gem5 started Aug 13 2012 18:12:01
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:28
+gem5 executing on ribera.cs.wisc.edu
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 33399000 because target called exit()
+Exiting @ tick 31633000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index b337ea793..45395bf9c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000032                       # Nu
 sim_ticks                                    31633000                       # Number of ticks simulated
 final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 284864                       # Simulator instruction rate (inst/s)
-host_op_rate                                   284628                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1547353604                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219460                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                   3112                       # Simulator instruction rate (inst/s)
+host_op_rate                                     3112                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               16931146                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270356                       # Number of bytes of host memory used
+host_seconds                                     1.87                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -146,104 +146,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.492114                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1950                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  14.130435                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.492114                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021360                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021360                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1950                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1950                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1950                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1950                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           51                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
-system.cpu.dcache.overall_misses::total           138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4785000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4785000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2805000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2805000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074807                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.074807                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.066092                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4611000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4611000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2703000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2703000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.114191                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
@@ -369,5 +271,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.tagsinuse                 87.492114                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1950                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.130435                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data      87.492114                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1950                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1950                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1950                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1950                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           51                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.dcache.overall_misses::total           138                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4785000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4785000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2805000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2805000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7590000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7590000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7590000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074807                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074807                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4611000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4611000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2703000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2703000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------