Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.

3 files changed, 38 insertions, 38 deletions

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index f7cc4efef..1e54677ab 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index ac53df969..3ee3fb923 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:58:11
-gem5 started Jun  4 2012 14:43:48
+gem5 compiled Jul  2 2012 08:47:33
+gem5 started Jul  2 2012 11:29:16
 gem5 executing on zizzer
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 32088000 because target called exit()
+Exiting @ tick 33413000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 8f49928a9..eb8915cb4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000032                       # Number of seconds simulated
-sim_ticks                                    32088000                       # Number of ticks simulated
-final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000033                       # Number of seconds simulated
+sim_ticks                                    33413000                       # Number of ticks simulated
+final_tick                                   33413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 540307                       # Simulator instruction rate (inst/s)
-host_op_rate                                   539410                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2965678153                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215020                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 168189                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168105                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              963489284                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219036                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            600349040                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            275243082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               875592122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       600349040                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          600349040                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           600349040                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           275243082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              875592122                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            576542064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            264328255                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               840870320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       576542064                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          576542064                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           576542064                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           264328255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              840870320                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,7 +46,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            64176                       # number of cpu cycles simulated
+system.cpu.numCycles                            66826                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5827                       # Number of instructions committed
@@ -65,18 +65,18 @@ system.cpu.num_mem_refs                          2090                       # nu
 system.cpu.num_load_insts                        1164                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      64176                       # Number of busy cycles
+system.cpu.num_busy_cycles                      66826                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                132.493866                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                133.092783                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5526                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.237624                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     132.493866                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.064694                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.064694                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     133.092783                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.064987                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.064987                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5526                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5526                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5526                       # number of demand (read+write) hits
@@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.458397                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 87.717237                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1951                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  14.137681                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.458397                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021352                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021352                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      87.717237                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021415                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021415                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1077                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1077                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
@@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.045319                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               188.818071                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    133.837577                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     54.207742                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004084                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001654                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005739                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    134.446837                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.371234                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004103                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001659                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005762                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits