diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
| commit | d7c083864c85c3ab24b40fc85ef3cae8031c5912 (patch) | |
| tree | ae575d831de5d67596ca3aae5e87a71f9c9fd1cd /tests/quick/se/00.hello/ref/mips/linux/simple-timing | |
| parent | 9b4249410ec18cac9df2c7e9c0a4a6ce5459233d (diff) | |
| download | gem5-d7c083864c85c3ab24b40fc85ef3cae8031c5912.tar.xz | |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing')
4 files changed, 142 insertions, 142 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index af5da1786..d2fab27ec 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -183,7 +181,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -218,6 +215,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -248,7 +246,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false @@ -283,6 +281,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr index 0f553ea6b..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 349ff71a4..c38df8b63 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:13 -gem5 executing on zizzer, pid 60580 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29861 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 33912500 because target called exit() +Exiting @ tick 33932500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index be6c762f8..dc14a2b12 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33912500 # Number of ticks simulated -final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 33932500 # Number of ticks simulated +final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109628 # Simulator instruction rate (inst/s) -host_op_rate 109584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 660533411 # Simulator tick rate (ticks/s) -host_mem_usage 228304 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 42153 # Simulator instruction rate (inst/s) +host_op_rate 42149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 253513577 # Simulator tick rate (ticks/s) +host_mem_usage 224784 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,87 +49,87 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 67825 # number of cpu cycles simulated +system.cpu.numCycles 67865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 67825 # Number of busy cycles +system.cpu.num_busy_cycles 67865 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.op_class::total 5642 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses @@ -146,22 +146,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 8494000 system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency @@ -194,14 +194,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency @@ -212,26 +212,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11547 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits -system.cpu.icache.overall_hits::total 5331 # number of overall hits +system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11581 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits +system.cpu.icache.overall_hits::total 5348 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses @@ -244,18 +244,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18192500 system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency @@ -284,12 +284,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency @@ -298,16 +298,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id |