diff options
| author | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
| commit | 4a644767c58754339965cecc5d85853255652a30 (patch) | |
| tree | e435caa3b1ba7f5e395c58ca0fdfdfa91804d2dd /tests/quick/se/00.hello/ref/mips/linux | |
| parent | 55411f7f713a42f67552a9621051fae8f7869648 (diff) | |
| download | gem5-4a644767c58754339965cecc5d85853255652a30.tar.xz | |
stats: update stats for no_value -> nan
Lots of accumulated older changes too.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux')
15 files changed, 156 insertions, 144 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 600677fb9..6db06c5ff 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=MipsTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts @@ -155,7 +152,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index e34fa5006..8cbac12cb 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:16:48 -gem5 started Feb 12 2012 18:16:47 -gem5 executing on zizzer -command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing +gem5 compiled May 8 2012 15:07:01 +gem5 started May 8 2012 15:36:45 +gem5 executing on piton +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index e8bd2f84c..2d3519846 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19775000 # Number of ticks simulated final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108846 # Simulator instruction rate (inst/s) -host_op_rate 108810 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 369151681 # Simulator tick rate (ticks/s) -host_mem_usage 210376 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 83973 # Simulator instruction rate (inst/s) +host_op_rate 83956 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 284866754 # Simulator tick rate (ticks/s) +host_mem_usage 214812 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory @@ -42,30 +42,6 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 39551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. -system.cpu.activity 13.572350 # Percentage of cycles cpu is active -system.cpu.comLoads 1164 # Number of Load instructions committed -system.cpu.comStores 925 # Number of Store instructions committed -system.cpu.comBranches 916 # Number of Branches instructions committed -system.cpu.comNops 657 # Number of Nop instructions committed -system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed -system.cpu.comInts 2155 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 1152 # Number of BP lookups system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect @@ -92,6 +68,30 @@ system.cpu.execution_unit.mispredictPct 65.065502 # Pe system.cpu.execution_unit.executions 3155 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. +system.cpu.activity 13.572350 # Percentage of cycles cpu is active +system.cpu.comLoads 1164 # Number of Load instructions committed +system.cpu.comStores 925 # Number of Store instructions committed +system.cpu.comBranches 916 # Number of Branches instructions committed +system.cpu.comNops 657 # Number of Nop instructions committed +system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed +system.cpu.comInts 2155 # Number of Integer instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed +system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) +system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). @@ -150,7 +150,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -232,7 +232,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -337,8 +337,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 00305a8e7..5535b7c1b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU @@ -127,7 +126,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -148,7 +147,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=MipsTLB @@ -419,7 +418,7 @@ opLat=3 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -440,7 +439,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts @@ -451,7 +450,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -471,8 +470,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -482,7 +481,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -514,15 +514,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index e545392ce..6efd85bce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:16:48 -gem5 started Feb 12 2012 18:16:57 -gem5 executing on zizzer -command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing +gem5 compiled May 8 2012 15:07:01 +gem5 started May 8 2012 15:36:45 +gem5 executing on piton +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index f9bef2483..0f84e872e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000013 # Nu sim_ticks 12671500 # Number of ticks simulated final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93816 # Simulator instruction rate (inst/s) -host_op_rate 93786 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 229841550 # Simulator tick rate (ticks/s) -host_mem_usage 211032 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 56172 # Simulator instruction rate (inst/s) +host_op_rate 56163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137660070 # Simulator tick rate (ticks/s) +host_mem_usage 215596 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30912 # Number of bytes read from this memory @@ -349,8 +349,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits @@ -431,8 +431,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits @@ -536,8 +536,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 9563d85bf..b0d54d9f2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=MipsTLB @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 7716b33a4..289fd9d0d 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:41 -gem5 executing on zizzer -command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic +gem5 compiled May 8 2012 15:07:01 +gem5 started May 8 2012 15:36:45 +gem5 executing on piton +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 9ae16c4c6..91924afa4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2913500 # Number of ticks simulated final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1078442 # Simulator instruction rate (inst/s) -host_op_rate 1075012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 535874927 # Simulator tick rate (ticks/s) -host_mem_usage 200784 # Number of bytes of host memory used +host_inst_rate 826404 # Simulator instruction rate (inst/s) +host_op_rate 824787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 411656542 # Simulator tick rate (ticks/s) +host_mem_usage 205596 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index da3c93787..c2b4be60f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.sys_port_proxy.port[0] +system_port=system.sys_port_proxy.slave[0] [system.cpu] type=TimingSimpleCPU @@ -54,8 +53,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.slave[1] +icache_port=system.l1_cntrl0.sequencer.slave[0] [system.cpu.dtb] type=MipsTLB @@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.cacheMemory max_outstanding_requests=16 -physmem=system.physmem ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system using_network_tester=false using_ruby_tester=false version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port +slave=system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30 latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort [system.ruby] type=RubySystem @@ -272,11 +273,12 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true -physmem=system.physmem ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system using_network_tester=false using_ruby_tester=false version=0 -physMemPort=system.physmem.port[1] -port=system.system_port +slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index ac3ff100c..4fad25b5f 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:52 -gem5 executing on zizzer -command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby +gem5 compiled May 8 2012 15:07:01 +gem5 started May 8 2012 15:36:45 +gem5 executing on piton +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 8087912dc..b950c6483 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000293 # Nu sim_ticks 292960 # Number of ticks simulated final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 71598 # Simulator instruction rate (inst/s) -host_op_rate 71583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3598224 # Simulator tick rate (ticks/s) -host_mem_usage 221836 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 60937 # Simulator instruction rate (inst/s) +host_op_rate 60929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3062846 # Simulator tick rate (ticks/s) +host_mem_usage 226192 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27687 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index 3cd70d03a..c6b1fd816 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=MipsTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 29b03eaff..0276ca4b7 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:50 -gem5 executing on zizzer -command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing +gem5 compiled May 8 2012 15:07:01 +gem5 started May 8 2012 15:36:45 +gem5 executing on piton +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 5a0520753..6c79a4c95 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 603210 # Simulator instruction rate (inst/s) -host_op_rate 602100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3309896144 # Simulator tick rate (ticks/s) -host_mem_usage 209992 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 273601 # Simulator instruction rate (inst/s) +host_op_rate 273420 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504754975 # Simulator tick rate (ticks/s) +host_mem_usage 214572 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28096 # Number of bytes read from this memory @@ -104,8 +104,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses @@ -180,8 +180,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses @@ -277,8 +277,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses |