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authorNilay Vaish <nilay@cs.wisc.edu>2014-02-24 20:50:06 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-02-24 20:50:06 -0600
commit53f697a6166a6fe2787882f3448e73a8ebb849aa (patch)
tree34375d648a60551f8a1ccb0a4486a35665b5115a /tests/quick/se/00.hello/ref/mips
parent8504b079b8e1c5bc4c14fa42ba224fe182ca43df (diff)
downloadgem5-53f697a6166a6fe2787882f3448e73a8ebb849aa.tar.xz
stats: updates due to c0db268f811b
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips')
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini20
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt10
2 files changed, 23 insertions, 7 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index d40656fb3..bb822211b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
+children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@@ -110,7 +112,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -133,6 +135,16 @@ latency_var=0
null=true
range=0:134217727
+[system.piobus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=false
+width=8
+master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
+slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
+
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@@ -252,6 +264,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
+mem_master_port=system.piobus.slave[1]
+pio_master_port=system.piobus.slave[0]
+pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@@ -346,7 +361,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 12d80d974..debae8203 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,15 +4,17 @@ sim_seconds 0.000125 # Nu
sim_ticks 125334 # Number of ticks simulated
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 31744 # Simulator instruction rate (inst/s)
-host_op_rate 31741 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 684175 # Simulator tick rate (ticks/s)
-host_mem_usage 176152 # Number of bytes of host memory used
+host_inst_rate 32356 # Simulator instruction rate (inst/s)
+host_op_rate 32352 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 697352 # Simulator tick rate (ticks/s)
+host_mem_usage 176168 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.piobus.throughput 0 # Throughput (bytes/s)
+system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message