diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/00.hello/ref/mips | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips')
3 files changed, 765 insertions, 750 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1593f969f..a18a67ef2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24417000 # Number of ticks simulated -final_tick 24417000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24407000 # Number of ticks simulated +final_tick 24407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26948 # Simulator instruction rate (inst/s) -host_op_rate 26945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116974890 # Simulator tick rate (ticks/s) -host_mem_usage 277212 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 92117 # Simulator instruction rate (inst/s) +host_op_rate 92097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399597243 # Simulator tick rate (ticks/s) +host_mem_usage 289532 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 820412008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359094074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1179506082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 820412008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359094074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1179506082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 820748146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359241201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1179989347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 820748146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359241201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1179989347 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 450 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24336000 # Total gap between requests +system.physmem.totGap 24326000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # By system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 4914500 # Total ticks spent queuing -system.physmem.totMemAccLat 13352000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4895500 # Total ticks spent queuing +system.physmem.totMemAccLat 13333000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10921.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10878.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29671.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1179.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29628.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1179.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1179.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1179.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.21 # Data bus utilization in percentage -system.physmem.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.22 # Data bus utilization in percentage +system.physmem.busUtilRead 9.22 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,55 +220,36 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54080.00 # Average gap between requests +system.physmem.avgGap 54057.78 # Average gap between requests system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22851000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 181440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 99000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 772200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2652000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 14753880 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16048350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 18567450 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 21225525 # Total energy per rank (pJ) -system.physmem.averagePower::0 785.799080 # Core power per rank (mW) -system.physmem.averagePower::1 898.292335 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 450 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 450 # Request fanout histogram -system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4210750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14753880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1232250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 18564450 # Total energy per rank (pJ) +system.physmem_0.averagePower 785.838404 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1971000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 582120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 317625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16041510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 99750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21218685 # Total energy per rank (pJ) +system.physmem_1.averagePower 898.383064 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 96500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1124 # Number of BP lookups system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -297,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 48835 # number of cpu cycles simulated +system.cpu.numCycles 48815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). @@ -322,9 +304,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43587 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 43567 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. -system.cpu.activity 10.746391 # Percentage of cycles cpu is active +system.cpu.activity 10.750794 # Percentage of cycles cpu is active system.cpu.comLoads 1132 # Number of Load instructions committed system.cpu.comStores 901 # Number of Store instructions committed system.cpu.comBranches 883 # Number of Branches instructions committed @@ -336,36 +318,148 @@ system.cpu.committedInsts 5624 # Nu system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) -system.cpu.cpi 8.683321 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.679765 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.683321 # CPI: Total CPI of All Threads -system.cpu.ipc 0.115163 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.679765 # CPI: Total CPI of All Threads +system.cpu.ipc 0.115210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.115163 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45291 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.115210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45271 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.257090 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46099 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.260064 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46079 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.602539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46145 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.604835 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46125 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.508344 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47641 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.510601 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47621 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.444968 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46041 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.445969 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46021 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.721306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.723651 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.114959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.114959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits +system.cpu.dcache.overall_hits::total 1596 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20579000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20579000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75430 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 147.900639 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.861470 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.900639 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.861470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072198 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -384,12 +478,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25151000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25136000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25136000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25136000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25136000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses @@ -402,12 +496,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73113.372093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73069.767442 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,64 +522,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 204.797884 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 204.748410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.365797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.432088 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.325774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.422636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006248 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id @@ -509,17 +575,17 @@ system.cpu.l2cache.demand_misses::total 450 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22634000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22619000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6609750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29243750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10333250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32967250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10333250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32967250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29228750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22619000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10328250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32947250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22619000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10328250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32947250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -542,17 +608,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995575 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993651 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995575 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74370 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74370 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +638,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18689500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24234750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18704000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8623750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27327750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18704000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8623750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27327750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24220250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18689500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8618750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27308250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18689500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8618750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27308250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -594,129 +660,68 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995575 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.129655 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.129655 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits -system.cpu.dcache.overall_hits::total 1596 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27952000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27952000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 450 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 450 # Request fanout histogram +system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4210250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 61d4efb5a..ca0260a61 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21163500 # Number of ticks simulated final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24711 # Simulator instruction rate (inst/s) -host_op_rate 24708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104867636 # Simulator tick rate (ticks/s) -host_mem_usage 278232 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 81533 # Simulator instruction rate (inst/s) +host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345921870 # Simulator tick rate (ticks/s) +host_mem_usage 292088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 75.58 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 44762.21 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) -system.physmem.averagePower::0 790.713406 # Core power per rank (mW) -system.physmem.averagePower::1 944.255803 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 421 # Transaction distribution -system.membus.trans_dist::ReadResp 421 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) +system.physmem_0.averagePower 790.660351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) +system.physmem_1.averagePower 944.255803 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2146 # Number of BP lookups system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_writes 5247 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. @@ -838,117 +904,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 471 # Request fanout histogram +system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 3a696e5a2..8476aa73a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000116 # Number of seconds simulated -sim_ticks 115508 # Number of ticks simulated -final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000115 # Number of seconds simulated +sim_ticks 115467 # Number of ticks simulated +final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2198 # Simulator instruction rate (inst/s) -host_op_rate 2198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45146 # Simulator tick rate (ticks/s) -host_mem_usage 435400 # Number of bytes of host memory used -host_seconds 2.56 # Real time elapsed on the host +host_inst_rate 66709 # Simulator instruction rate (inst/s) +host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369179 # Simulator tick rate (ticks/s) +host_mem_usage 449556 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,41 +21,41 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts @@ -64,16 +64,16 @@ system.mem_ctrls.perBankWrBursts::5 3 # Pe system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115437 # Total gap between requests +system.mem_ctrls.totGap 115396 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,12 +135,12 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see @@ -184,162 +184,91 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12468 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12340 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.32 # Average gap between requests -system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2936 # delay histogram for all message -system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2936 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7659 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.083312 -system.ruby.latency_hist::gmean 5.240199 -system.ruby.latency_hist::stdev 27.247033 -system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7658 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6188 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.738776 -system.ruby.miss_latency_hist::gmean 54.828482 -system.ruby.miss_latency_hist::stdev 34.263958 -system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1470 -system.ruby.Directory.incomplete_times 1469 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.30 # Average gap between requests +system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.354538 -system.ruby.network.routers0.msg_count.Control::2 1470 -system.ruby.network.routers0.msg_count.Data::2 1466 -system.ruby.network.routers0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.msg_bytes.Control::2 11760 -system.ruby.network.routers0.msg_bytes.Data::2 105552 -system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.354538 -system.ruby.network.routers1.msg_count.Control::2 1470 -system.ruby.network.routers1.msg_count.Data::2 1466 -system.ruby.network.routers1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.msg_bytes.Control::2 11760 -system.ruby.network.routers1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.354538 -system.ruby.network.routers2.msg_count.Control::2 1470 -system.ruby.network.routers2.msg_count.Data::2 1466 -system.ruby.network.routers2.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.msg_bytes.Control::2 11760 -system.ruby.network.routers2.msg_bytes.Data::2 105552 -system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.msg_count.Control 4410 -system.ruby.network.msg_count.Data 4398 -system.ruby.network.msg_count.Response_Data 4410 -system.ruby.network.msg_count.Writeback_Control 4398 -system.ruby.network.msg_byte.Control 35280 -system.ruby.network.msg_byte.Data 316656 -system.ruby.network.msg_byte.Response_Data 317520 -system.ruby.network.msg_byte.Writeback_Control 35184 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -359,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115508 # number of cpu cycles simulated +system.cpu.numCycles 115467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -378,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115508 # Number of busy cycles +system.cpu.num_busy_cycles 115467 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -417,32 +346,108 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.361464 +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 2936 # delay histogram for all message +system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2936 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 7659 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 7659 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 7658 +system.ruby.latency_hist::mean 14.077958 +system.ruby.latency_hist::gmean 5.242569 +system.ruby.latency_hist::stdev 26.858459 +system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 7658 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6188 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6188 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1470 +system.ruby.miss_latency_hist::mean 60.710884 +system.ruby.miss_latency_hist::gmean 54.957755 +system.ruby.miss_latency_hist::stdev 32.665540 +system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1470 +system.ruby.Directory.incomplete_times 1469 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.msg_count.Control::2 1470 +system.ruby.network.routers0.msg_count.Data::2 1466 +system.ruby.network.routers0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.msg_bytes.Control::2 11760 +system.ruby.network.routers0.msg_bytes.Data::2 105552 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.msg_count.Control::2 1470 +system.ruby.network.routers1.msg_count.Data::2 1466 +system.ruby.network.routers1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.msg_bytes.Control::2 11760 +system.ruby.network.routers1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.msg_count.Control::2 1470 +system.ruby.network.routers2.msg_count.Data::2 1466 +system.ruby.network.routers2.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.msg_bytes.Control::2 11760 +system.ruby.network.routers2.msg_bytes.Data::2 105552 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.msg_count.Control 4410 +system.ruby.network.msg_count.Data 4398 +system.ruby.network.msg_count.Response_Data 4410 +system.ruby.network.msg_count.Writeback_Control 4398 +system.ruby.network.msg_byte.Control 35280 +system.ruby.network.msg_byte.Data 316656 +system.ruby.network.msg_byte.Response_Data 317520 +system.ruby.network.msg_byte.Writeback_Control 35184 +system.ruby.network.routers0.throttle0.link_utilization 6.363723 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.347612 +system.ruby.network.routers0.throttle1.link_utilization 6.349866 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.347612 +system.ruby.network.routers1.throttle0.link_utilization 6.349866 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.361464 +system.ruby.network.routers1.throttle1.link_utilization 6.363723 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.361464 +system.ruby.network.routers2.throttle0.link_utilization 6.363723 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.347612 +system.ruby.network.routers2.throttle1.link_utilization 6.349866 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -457,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.522968 -system.ruby.LD.latency_hist::gmean 16.130611 -system.ruby.LD.latency_hist::stdev 37.257775 -system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.492049 +system.ruby.LD.latency_hist::gmean 16.147834 +system.ruby.LD.latency_hist::stdev 37.303839 +system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -472,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 +system.ruby.LD.miss_latency_hist::bucket_size 32 +system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.196402 -system.ruby.LD.miss_latency_hist::gmean 52.112336 -system.ruby.LD.miss_latency_hist::stdev 33.226027 -system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.143928 +system.ruby.LD.miss_latency_hist::gmean 52.206801 +system.ruby.LD.miss_latency_hist::stdev 33.349415 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::bucket_size 32 +system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 15.558269 -system.ruby.ST.latency_hist::gmean 5.883337 -system.ruby.ST.latency_hist::stdev 27.738104 -system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.748058 +system.ruby.ST.latency_hist::gmean 5.824702 +system.ruby.ST.latency_hist::stdev 24.783906 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -495,21 +500,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 +system.ruby.ST.miss_latency_hist::bucket_size 32 +system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 55.142857 -system.ruby.ST.miss_latency_hist::gmean 49.160125 -system.ruby.ST.miss_latency_hist::stdev 33.648687 -system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.778802 +system.ruby.ST.miss_latency_hist::gmean 47.157588 +system.ruby.ST.miss_latency_hist::stdev 27.288529 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 217 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.532444 -system.ruby.IFETCH.latency_hist::gmean 4.102291 -system.ruby.IFETCH.latency_hist::stdev 22.246367 -system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.661156 +system.ruby.IFETCH.latency_hist::gmean 4.110524 +system.ruby.IFETCH.latency_hist::stdev 22.183687 +system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -521,18 +526,18 @@ system.ruby.IFETCH.hit_latency_hist::total 5039 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 65.704778 -system.ruby.IFETCH.miss_latency_hist::gmean 60.488386 -system.ruby.IFETCH.miss_latency_hist::stdev 35.064530 -system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 66.940273 +system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 +system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 +system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.738776 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482 -system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958 -system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 +system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -560,30 +565,38 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% @@ -600,13 +613,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% ---------- End Simulation Statistics ---------- |